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Mingkai Hu4f1d1b72011-07-07 12:29:15 +08001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2011-2012 Freescale Semiconductor, Inc.
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08003 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hu4f1d1b72011-07-07 12:29:15 +08005 */
6
7/*
8 * P2041 RDB board configuration file
Scott Wood3e978f52012-08-14 10:14:51 +00009 * Also supports P2040 RDB
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14#define CONFIG_P2041RDB
15#define CONFIG_PHYS_64BIT
16#define CONFIG_PPC_P2041
17
18#ifdef CONFIG_RAMBOOT_PBL
19#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
20#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090021#define CONFIG_SYS_FSL_PBL_PBI board/freescale/corenet_ds/pbi.cfg
22#define CONFIG_SYS_FSL_PBL_RCW board/freescale/corenet_ds/rcw_p2041rdb.cfg
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080023#endif
24
Liu Gang461632b2012-08-09 05:10:03 +000025#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
Liu Gangff65f122012-08-09 05:09:59 +000026/* Set 1M boot space */
Liu Gang461632b2012-08-09 05:10:03 +000027#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
28#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
29 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
Liu Gangff65f122012-08-09 05:09:59 +000030#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
31#define CONFIG_SYS_NO_FLASH
32#endif
33
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080034/* High Level Configuration Options */
35#define CONFIG_BOOKE
36#define CONFIG_E500 /* BOOKE e500 family */
37#define CONFIG_E500MC /* BOOKE e500mc family */
38#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080039#define CONFIG_MP /* support multiple processors */
40
41#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053042#define CONFIG_SYS_TEXT_BASE 0xeff40000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080043#endif
44
45#ifndef CONFIG_RESET_VECTOR_ADDRESS
46#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
47#endif
48
49#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
50#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
51#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
52#define CONFIG_PCI /* Enable PCI/PCIE */
53#define CONFIG_PCIE1 /* PCIE controler 1 */
54#define CONFIG_PCIE2 /* PCIE controler 2 */
55#define CONFIG_PCIE3 /* PCIE controler 3 */
56#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
57#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
58
59#define CONFIG_SYS_SRIO
60#define CONFIG_SRIO1 /* SRIO port 1 */
61#define CONFIG_SRIO2 /* SRIO port 2 */
Liu Gangc8b28152013-05-07 16:30:46 +080062#define CONFIG_SRIO_PCIE_BOOT_MASTER
Kumar Gala4d28db82011-10-14 13:28:52 -050063#define CONFIG_SYS_DPAA_RMAN /* RMan */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080064
65#define CONFIG_FSL_LAW /* Use common FSL init code */
66
67#define CONFIG_ENV_OVERWRITE
68
69#ifdef CONFIG_SYS_NO_FLASH
Liu Gang461632b2012-08-09 05:10:03 +000070#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080071#define CONFIG_ENV_IS_NOWHERE
Shaohui Xie0f57f6a2012-06-28 23:35:34 +000072#endif
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080073#else
74#define CONFIG_FLASH_CFI_DRIVER
75#define CONFIG_SYS_FLASH_CFI
Shaohui Xie0f57f6a2012-06-28 23:35:34 +000076#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080077#endif
78
79#if defined(CONFIG_SPIFLASH)
80 #define CONFIG_SYS_EXTRA_ENV_RELOC
81 #define CONFIG_ENV_IS_IN_SPI_FLASH
82 #define CONFIG_ENV_SPI_BUS 0
83 #define CONFIG_ENV_SPI_CS 0
84 #define CONFIG_ENV_SPI_MAX_HZ 10000000
85 #define CONFIG_ENV_SPI_MODE 0
86 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
87 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
88 #define CONFIG_ENV_SECT_SIZE 0x10000
89#elif defined(CONFIG_SDCARD)
90 #define CONFIG_SYS_EXTRA_ENV_RELOC
91 #define CONFIG_ENV_IS_IN_MMC
Fabio Estevam4394d0c2012-01-11 09:20:50 +000092 #define CONFIG_FSL_FIXED_MMC_LOCATION
Mingkai Hu4f1d1b72011-07-07 12:29:15 +080093 #define CONFIG_SYS_MMC_ENV_DEV 0
94 #define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053095 #define CONFIG_ENV_OFFSET (512 * 1658)
Shaohui Xie15c8c6c2012-02-28 23:28:40 +000096#elif defined(CONFIG_NAND)
97#define CONFIG_SYS_EXTRA_ENV_RELOC
98#define CONFIG_ENV_IS_IN_NAND
99#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530100#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang461632b2012-08-09 05:10:03 +0000101#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gangff65f122012-08-09 05:09:59 +0000102#define CONFIG_ENV_IS_IN_REMOTE
103#define CONFIG_ENV_ADDR 0xffe20000
104#define CONFIG_ENV_SIZE 0x2000
Shaohui Xie0f57f6a2012-06-28 23:35:34 +0000105#elif defined(CONFIG_ENV_IS_NOWHERE)
Liu Gangff65f122012-08-09 05:09:59 +0000106#define CONFIG_ENV_SIZE 0x2000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800107#else
108 #define CONFIG_ENV_IS_IN_FLASH
109 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \
110 - CONFIG_ENV_SECT_SIZE)
111 #define CONFIG_ENV_SIZE 0x2000
112 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
113#endif
114
Shaohui Xie44d50f02011-09-13 17:55:11 +0800115#ifndef __ASSEMBLY__
116unsigned long get_board_sys_clk(unsigned long dummy);
117#endif
118#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800119
120/*
121 * These can be toggled for performance analysis, otherwise use default.
122 */
123#define CONFIG_SYS_CACHE_STASHING
Mingkai Hucd420e02011-07-21 17:03:54 -0500124#define CONFIG_BACKSIDE_L2_CACHE
125#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800126#define CONFIG_BTB /* toggle branch predition */
127
128#define CONFIG_ENABLE_36BIT_PHYS
129
130#ifdef CONFIG_PHYS_64BIT
131#define CONFIG_ADDR_MAP
132#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
133#endif
134
135#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */
136#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
137#define CONFIG_SYS_MEMTEST_END 0x00400000
138#define CONFIG_SYS_ALT_MEMTEST
139#define CONFIG_PANIC_HANG /* do not reset board on panic */
140
141/*
142 * Config the L3 Cache as L3 SRAM
143 */
144#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
145#ifdef CONFIG_PHYS_64BIT
146#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | \
147 CONFIG_RAMBOOT_TEXT_BASE)
148#else
149#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
150#endif
151#define CONFIG_SYS_L3_SIZE (1024 << 10)
152#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
153
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800154#ifdef CONFIG_PHYS_64BIT
155#define CONFIG_SYS_DCSRBAR 0xf0000000
156#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
157#endif
158
159/* EEPROM */
160#define CONFIG_ID_EEPROM
161#define CONFIG_SYS_I2C_EEPROM_NXID
162#define CONFIG_SYS_EEPROM_BUS_NUM 0
163#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
164#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
165
166/*
167 * DDR Setup
168 */
169#define CONFIG_VERY_BIG_RAM
170#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
171#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
172
173#define CONFIG_DIMM_SLOTS_PER_CTLR 1
174#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
175
176#define CONFIG_DDR_SPD
York Sun5614e712013-09-30 09:22:09 -0700177#define CONFIG_SYS_FSL_DDR3
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800178
179#define CONFIG_SYS_SPD_BUS_NUM 0
180#define SPD_EEPROM_ADDRESS 0x52
181#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
182
183/*
184 * Local Bus Definitions
185 */
186
187/* Set the local bus clock 1/8 of platform clock */
188#define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8
189
York Sunca1b0b82012-10-26 16:40:15 +0000190/*
191 * This board doesn't have a promjet connector.
192 * However, it uses commone corenet board LAW and TLB.
193 * It is necessary to use the same start address with proper offset.
194 */
195#define CONFIG_SYS_FLASH_BASE 0xe0000000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800196#ifdef CONFIG_PHYS_64BIT
York Sunca1b0b82012-10-26 16:40:15 +0000197#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800198#else
199#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
200#endif
201
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000202#define CONFIG_SYS_FLASH_BR_PRELIM \
York Sunca1b0b82012-10-26 16:40:15 +0000203 (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
204 BR_PS_16 | BR_V)
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000205#define CONFIG_SYS_FLASH_OR_PRELIM \
206 ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
207 | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800208
209#define CONFIG_FSL_CPLD
210#define CPLD_BASE 0xffdf0000 /* CPLD registers */
211#ifdef CONFIG_PHYS_64BIT
212#define CPLD_BASE_PHYS 0xfffdf0000ull
213#else
214#define CPLD_BASE_PHYS CPLD_BASE
215#endif
216
217#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
218#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
219
220#define PIXIS_LBMAP_SWITCH 7
221#define PIXIS_LBMAP_MASK 0xf0
222#define PIXIS_LBMAP_SHIFT 4
223#define PIXIS_LBMAP_ALTBANK 0x40
224
225#define CONFIG_SYS_FLASH_QUIET_TEST
226#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
227
228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
229#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
230#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */
231#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */
232
233#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
234
235#if defined(CONFIG_RAMBOOT_PBL)
236#define CONFIG_SYS_RAMBOOT
237#endif
238
Shaohui Xiec9b2fea2012-02-28 23:28:07 +0000239#define CONFIG_NAND_FSL_ELBC
240/* Nand Flash */
241#ifdef CONFIG_NAND_FSL_ELBC
242#define CONFIG_SYS_NAND_BASE 0xffa00000
243#ifdef CONFIG_PHYS_64BIT
244#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
245#else
246#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
247#endif
248
249#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
250#define CONFIG_SYS_MAX_NAND_DEVICE 1
251#define CONFIG_MTD_NAND_VERIFY_WRITE
252#define CONFIG_CMD_NAND
253#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
254
255/* NAND flash config */
256#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
257 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
258 | BR_PS_8 /* Port Size = 8 bit */ \
259 | BR_MS_FCM /* MSEL = FCM */ \
260 | BR_V) /* valid */
261#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
262 | OR_FCM_PGS /* Large Page*/ \
263 | OR_FCM_CSCT \
264 | OR_FCM_CST \
265 | OR_FCM_CHT \
266 | OR_FCM_SCY_1 \
267 | OR_FCM_TRLX \
268 | OR_FCM_EHTR)
269
270#ifdef CONFIG_NAND
271#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
272#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
273#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
274#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
275#else
276#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
277#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
278#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
279#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
280#endif
281#else
282#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
283#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
284#endif /* CONFIG_NAND_FSL_ELBC */
285
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800286#define CONFIG_SYS_FLASH_EMPTY_INFO
287#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
York Sunca1b0b82012-10-26 16:40:15 +0000288#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800289
290#define CONFIG_BOARD_EARLY_INIT_F
291#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
292#define CONFIG_MISC_INIT_R
293
294#define CONFIG_HWCONFIG
295
296/* define to use L1 as initial stack */
297#define CONFIG_L1_INIT_RAM
298#define CONFIG_SYS_INIT_RAM_LOCK
299#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
300#ifdef CONFIG_PHYS_64BIT
301#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
302#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
303/* The assembler doesn't like typecast */
304#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
305 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
306 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
307#else
308#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
309#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
310#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
311#endif
312#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
313
314#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
315 GENERATED_GBL_DATA_SIZE)
316#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
317
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530318#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800319#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
320
321/* Serial Port - controlled on board with jumper J8
322 * open - index 2
323 * shorted - index 1
324 */
325#define CONFIG_CONS_INDEX 1
326#define CONFIG_SYS_NS16550
327#define CONFIG_SYS_NS16550_SERIAL
328#define CONFIG_SYS_NS16550_REG_SIZE 1
329#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
330
331#define CONFIG_SYS_BAUDRATE_TABLE \
332 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
333
334#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
335#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
336#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
337#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
338
339/* Use the HUSH parser */
340#define CONFIG_SYS_HUSH_PARSER
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800341
342/* pass open firmware flat tree */
343#define CONFIG_OF_LIBFDT
344#define CONFIG_OF_BOARD_SETUP
345#define CONFIG_OF_STDOUT_VIA_ALIAS
346
347/* new uImage format support */
348#define CONFIG_FIT
349#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
350
351/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200352#define CONFIG_SYS_I2C
353#define CONFIG_SYS_I2C_FSL
354#define CONFIG_SYS_FSL_I2C_SPEED 400000
355#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Shaohui Xie2bd1aab2013-09-10 16:15:07 +0800356#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Heiko Schocher00f792e2012-10-24 13:48:22 +0200357#define CONFIG_SYS_FSL_I2C2_SPEED 400000
358#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shaohui Xie2bd1aab2013-09-10 16:15:07 +0800359#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800360
361/*
362 * RapidIO
363 */
364#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
365#ifdef CONFIG_PHYS_64BIT
366#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
367#else
368#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
369#endif
370#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
371
372#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
373#ifdef CONFIG_PHYS_64BIT
374#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
375#else
376#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
377#endif
378#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
379
380/*
Liu Gangff65f122012-08-09 05:09:59 +0000381 * for slave u-boot IMAGE instored in master memory space,
382 * PHYS must be aligned based on the SIZE
383 */
Liu Gange4911812014-05-15 14:30:34 +0800384#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
385#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
386#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
387#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Liu Gangff65f122012-08-09 05:09:59 +0000388/*
389 * for slave UCODE and ENV instored in master memory space,
390 * PHYS must be aligned based on the SIZE
391 */
Liu Gange4911812014-05-15 14:30:34 +0800392#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Liu Gangb5f7c872012-08-09 05:10:02 +0000393#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
394#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
Liu Gangff65f122012-08-09 05:09:59 +0000395
396/* slave core release by master*/
Liu Gangb5f7c872012-08-09 05:10:02 +0000397#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
398#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
Liu Gangff65f122012-08-09 05:09:59 +0000399
400/*
Liu Gang461632b2012-08-09 05:10:03 +0000401 * SRIO_PCIE_BOOT - SLAVE
Liu Gangff65f122012-08-09 05:09:59 +0000402 */
Liu Gang461632b2012-08-09 05:10:03 +0000403#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
404#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
405#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
406 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
Liu Gangff65f122012-08-09 05:09:59 +0000407#endif
408
409/*
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800410 * eSPI - Enhanced SPI
411 */
412#define CONFIG_FSL_ESPI
413#define CONFIG_SPI_FLASH
414#define CONFIG_SPI_FLASH_SPANSION
415#define CONFIG_CMD_SF
416#define CONFIG_SF_DEFAULT_SPEED 10000000
417#define CONFIG_SF_DEFAULT_MODE 0
418
419/*
420 * General PCI
421 * Memory space is mapped 1-1, but I/O space must start from 0.
422 */
423
424/* controller 1, direct to uli, tgtid 3, Base address 20000 */
425#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
426#ifdef CONFIG_PHYS_64BIT
427#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
428#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
429#else
430#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
431#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
432#endif
433#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
434#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
435#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
436#ifdef CONFIG_PHYS_64BIT
437#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
438#else
439#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
440#endif
441#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
442
443/* controller 2, Slot 2, tgtid 2, Base address 201000 */
444#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
445#ifdef CONFIG_PHYS_64BIT
446#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
447#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
448#else
449#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
450#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
451#endif
452#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
453#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
454#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
455#ifdef CONFIG_PHYS_64BIT
456#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
457#else
458#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
459#endif
460#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
461
462/* controller 3, Slot 1, tgtid 1, Base address 202000 */
463#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
464#ifdef CONFIG_PHYS_64BIT
465#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
466#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
467#else
468#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
469#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
470#endif
471#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
472#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
473#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
474#ifdef CONFIG_PHYS_64BIT
475#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
476#else
477#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
478#endif
479#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
480
481/* Qman/Bman */
482#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
483#define CONFIG_SYS_BMAN_NUM_PORTALS 10
484#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
485#ifdef CONFIG_PHYS_64BIT
486#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
487#else
488#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
489#endif
490#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
491#define CONFIG_SYS_QMAN_NUM_PORTALS 10
492#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
493#ifdef CONFIG_PHYS_64BIT
494#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
495#else
496#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
497#endif
498#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
499
500#define CONFIG_SYS_DPAA_FMAN
501#define CONFIG_SYS_DPAA_PME
502/* Default address of microcode for the Linux Fman driver */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800503#if defined(CONFIG_SPIFLASH)
504/*
505 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
506 * env, so we got 0x110000.
507 */
Timur Tabif2717b42011-11-22 09:21:25 -0600508#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800509#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800510#elif defined(CONFIG_SDCARD)
511/*
512 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530513 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
514 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800515 */
Timur Tabif2717b42011-11-22 09:21:25 -0600516#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800517#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800518#elif defined(CONFIG_NAND)
Timur Tabif2717b42011-11-22 09:21:25 -0600519#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800520#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Liu Gang461632b2012-08-09 05:10:03 +0000521#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
Liu Gangff65f122012-08-09 05:09:59 +0000522/*
523 * Slave has no ucode locally, it can fetch this from remote. When implementing
524 * in two corenet boards, slave's ucode could be stored in master's memory
525 * space, the address can be mapped from slave TLB->slave LAW->
Liu Gang461632b2012-08-09 05:10:03 +0000526 * slave SRIO or PCIE outbound window->master inbound window->
527 * master LAW->the ucode address in master's memory space.
Liu Gangff65f122012-08-09 05:09:59 +0000528 */
529#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800530#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800531#else
Timur Tabif2717b42011-11-22 09:21:25 -0600532#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800533#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800534#endif
Timur Tabif2717b42011-11-22 09:21:25 -0600535#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
536#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800537
538#ifdef CONFIG_SYS_DPAA_FMAN
539#define CONFIG_FMAN_ENET
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800540#define CONFIG_PHYLIB_10G
541#define CONFIG_PHY_VITESSE
542#define CONFIG_PHY_TERANETICS
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800543#endif
544
545#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000546#define CONFIG_PCI_INDIRECT_BRIDGE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800547#define CONFIG_PCI_PNP /* do pci plug-and-play */
548#define CONFIG_E1000
549
550#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
551#define CONFIG_DOS_PARTITION
552#endif /* CONFIG_PCI */
553
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800554/* SATA */
Zang Roy-R619119760b272012-11-26 00:05:38 +0000555#define CONFIG_FSL_SATA_V2
556
557#ifdef CONFIG_FSL_SATA_V2
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800558#define CONFIG_FSL_SATA
Timur Tabi3e0529f2011-11-21 17:10:22 -0600559#define CONFIG_LIBATA
Mingkai Huaa7f281c2011-07-27 09:55:51 +0800560
561#define CONFIG_SYS_SATA_MAX_DEVICE 2
562#define CONFIG_SATA1
563#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
564#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
565#define CONFIG_SATA2
566#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
567#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
568
569#define CONFIG_LBA48
570#define CONFIG_CMD_SATA
571#define CONFIG_DOS_PARTITION
572#define CONFIG_CMD_EXT2
573#endif
574
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800575#ifdef CONFIG_FMAN_ENET
576#define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2
577#define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x3
578#define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x4
579#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1
580#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x0
581
582#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
583#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
584#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
585#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
586
Mingkai Hu0787ecc2011-07-19 16:20:13 +0800587#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0
588
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800589#define CONFIG_SYS_TBIPA_VALUE 8
590#define CONFIG_MII /* MII PHY management */
591#define CONFIG_ETHPRIME "FM1@DTSEC1"
592#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
593#endif
594
595/*
596 * Environment
597 */
598#define CONFIG_LOADS_ECHO /* echo on for serial download */
599#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
600
601/*
602 * Command line configuration.
603 */
604#include <config_cmd_default.h>
605
606#define CONFIG_CMD_DHCP
607#define CONFIG_CMD_ELF
608#define CONFIG_CMD_ERRATA
609#define CONFIG_CMD_GREPENV
610#define CONFIG_CMD_IRQ
611#define CONFIG_CMD_I2C
612#define CONFIG_CMD_MII
613#define CONFIG_CMD_PING
614#define CONFIG_CMD_SETEXPR
615
616#ifdef CONFIG_PCI
617#define CONFIG_CMD_PCI
618#define CONFIG_CMD_NET
619#endif
620
621/*
622* USB
623*/
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000624#define CONFIG_HAS_FSL_DR_USB
625#define CONFIG_HAS_FSL_MPH_USB
626
627#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800628#define CONFIG_CMD_USB
629#define CONFIG_USB_STORAGE
630#define CONFIG_USB_EHCI
631#define CONFIG_USB_EHCI_FSL
632#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000633#endif
634
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800635#define CONFIG_CMD_EXT2
636
637#define CONFIG_MMC
638
639#ifdef CONFIG_MMC
640#define CONFIG_FSL_ESDHC
641#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
642#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
643#define CONFIG_CMD_MMC
644#define CONFIG_GENERIC_MMC
645#define CONFIG_CMD_EXT2
646#define CONFIG_CMD_FAT
647#define CONFIG_DOS_PARTITION
648#endif
649
650/*
651 * Miscellaneous configurable options
652 */
653#define CONFIG_SYS_LONGHELP /* undef to save memory */
654#define CONFIG_CMDLINE_EDITING /* Command-line editing */
655#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
656#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800657#ifdef CONFIG_CMD_KGDB
658#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
659#else
660#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
661#endif
662/* Print Buffer Size */
663#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
664 sizeof(CONFIG_SYS_PROMPT)+16)
665#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
666/* Boot Argument Buffer Size */
667#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800668
669/*
670 * For booting Linux, the board info and command line data
671 * have to be in the first 64 MB of memory, since this is
672 * the maximum mapped by the Linux kernel during initialization.
673 */
674#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */
675#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
676
677#ifdef CONFIG_CMD_KGDB
678#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800679#endif
680
681/*
682 * Environment Configuration
683 */
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000684#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000685#define CONFIG_BOOTFILE "uImage"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800686#define CONFIG_UBOOTPATH u-boot.bin
687
688/* default location for tftp and bootm */
689#define CONFIG_LOADADDR 1000000
690
691#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
692
693#define CONFIG_BAUDRATE 115200
694
695#define __USB_PHY_TYPE utmi
696
697#define CONFIG_EXTRA_ENV_SETTINGS \
698 "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
699 "bank_intlv=cs0_cs1\0" \
700 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200701 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
702 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800703 "tftpflash=tftpboot $loadaddr $uboot && " \
704 "protect off $ubootaddr +$filesize && " \
705 "erase $ubootaddr +$filesize && " \
706 "cp.b $loadaddr $ubootaddr $filesize && " \
707 "protect on $ubootaddr +$filesize && " \
708 "cmp.b $loadaddr $ubootaddr $filesize\0" \
709 "consoledev=ttyS0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200710 "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800711 "usb_dr_mode=host\0" \
712 "ramdiskaddr=2000000\0" \
713 "ramdiskfile=p2041rdb/ramdisk.uboot\0" \
714 "fdtaddr=c00000\0" \
715 "fdtfile=p2041rdb/p2041rdb.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500716 "bdev=sda3\0"
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800717
718#define CONFIG_HDBOOT \
719 "setenv bootargs root=/dev/$bdev rw " \
720 "console=$consoledev,$baudrate $othbootargs;" \
721 "tftp $loadaddr $bootfile;" \
722 "tftp $fdtaddr $fdtfile;" \
723 "bootm $loadaddr - $fdtaddr"
724
725#define CONFIG_NFSBOOTCOMMAND \
726 "setenv bootargs root=/dev/nfs rw " \
727 "nfsroot=$serverip:$rootpath " \
728 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
729 "console=$consoledev,$baudrate $othbootargs;" \
730 "tftp $loadaddr $bootfile;" \
731 "tftp $fdtaddr $fdtfile;" \
732 "bootm $loadaddr - $fdtaddr"
733
734#define CONFIG_RAMBOOTCOMMAND \
735 "setenv bootargs root=/dev/ram rw " \
736 "console=$consoledev,$baudrate $othbootargs;" \
737 "tftp $ramdiskaddr $ramdiskfile;" \
738 "tftp $loadaddr $bootfile;" \
739 "tftp $fdtaddr $fdtfile;" \
740 "bootm $loadaddr $ramdiskaddr $fdtaddr"
741
742#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
743
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800744#include <asm/fsl_secure_boot.h>
Mingkai Hu4f1d1b72011-07-07 12:29:15 +0800745
746#endif /* __CONFIG_H */