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Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +02001/*
2 * (C) Copyright 2006-2008
3 * Texas Instruments.
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Syed Mohammed Khasim <x0khasim@ti.com>
6 *
7 * (C) Copyright 2009
8 * Frederik Kriewitz <frederik@kriewitz.eu>
9 *
10 * Configuration settings for the DevKit8000 board.
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020033
34/* High Level Configuration Options */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020035#define CONFIG_OMAP 1 /* in a TI OMAP core */
36#define CONFIG_OMAP34XX 1 /* which is a 34XX */
37#define CONFIG_OMAP3430 1 /* which is in a 3430 */
38#define CONFIG_OMAP3_DEVKIT8000 1 /* working with DevKit8000 */
39
Thomas Weber66fca012010-10-18 15:38:15 +020040#define CONFIG_SYS_TEXT_BASE 0x80008000
41
Vaibhav Hiremathcae377b2010-06-07 15:20:34 -040042#define CONFIG_SDRC /* The chip has SDRC controller */
43
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020044#include <asm/arch/cpu.h> /* get chip and board defs */
45#include <asm/arch/omap3.h>
46
47/* Display CPU and Board information */
48#define CONFIG_DISPLAY_CPUINFO 1
49#define CONFIG_DISPLAY_BOARDINFO 1
50
51/* Clock Defines */
52#define V_OSCK 26000000 /* Clock output from T2 */
53#define V_SCLK (V_OSCK >> 1)
54
55#undef CONFIG_USE_IRQ /* no support for IRQs */
56#define CONFIG_MISC_INIT_R
57
58#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
59#define CONFIG_SETUP_MEMORY_TAGS 1
60#define CONFIG_INITRD_TAG 1
61#define CONFIG_REVISION_TAG 1
62
Grant Likely2fa8ca92011-03-28 09:59:07 +000063#define CONFIG_OF_LIBFDT 1
64
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020065/* Size of malloc() pool */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040066#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020067 /* Sector */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -040068#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020069
70/* Hardware drivers */
71
Nishanth Menon30563a02009-11-07 10:51:24 -050072/* DDR - I use Micron DDR */
73#define CONFIG_OMAP3_MICRON_DDR 1
74
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020075/* DM9000 */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +020076#define CONFIG_NET_RETRY_COUNT 20
77#define CONFIG_DRIVER_DM9000 1
78#define CONFIG_DM9000_BASE 0x2c000000
79#define DM9000_IO CONFIG_DM9000_BASE
80#define DM9000_DATA (CONFIG_DM9000_BASE + 0x400)
81#define CONFIG_DM9000_USE_16BIT 1
82#define CONFIG_DM9000_NO_SROM 1
83#undef CONFIG_DM9000_DEBUG
84
85/* NS16550 Configuration */
86#define CONFIG_SYS_NS16550
87#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE (-4)
89#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
90
91/* select serial console configuration */
92#define CONFIG_CONS_INDEX 3
93#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
94#define CONFIG_SERIAL3 3
95#define CONFIG_BAUDRATE 115200
96#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
97 115200}
98
99/* MMC */
Tom Rinif4085012011-09-03 21:52:45 -0400100#define CONFIG_GENERIC_MMC 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200101#define CONFIG_MMC 1
Tom Rinif4085012011-09-03 21:52:45 -0400102#define CONFIG_OMAP_HSMMC 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200103#define CONFIG_DOS_PARTITION 1
104
105/* I2C */
Tom Rix0297ec72009-09-29 10:19:49 -0400106#define CONFIG_HARD_I2C 1
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200107#define CONFIG_SYS_I2C_SPEED 100000
108#define CONFIG_SYS_I2C_SLAVE 1
109#define CONFIG_SYS_I2C_BUS 0
110#define CONFIG_SYS_I2C_BUS_SELECT 1
111#define CONFIG_DRIVER_OMAP34XX_I2C 1
112
113/* TWL4030 */
114#define CONFIG_TWL4030_POWER 1
115#define CONFIG_TWL4030_LED 1
116
117/* Board NAND Info */
118#define CONFIG_SYS_NO_FLASH /* no NOR flash */
119#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
120#define MTDIDS_DEFAULT "nand0=nand"
121#define MTDPARTS_DEFAULT "mtdparts=nand:" \
122 "512k(x-loader)," \
123 "1920k(u-boot)," \
124 "128k(u-boot-env)," \
125 "4m(kernel)," \
126 "-(fs)"
127
128#define CONFIG_NAND_OMAP_GPMC
129#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
130 /* to access nand */
131#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
132 /* to access nand at */
133 /* CS0 */
134#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
135
136#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
137 /* devices */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200138#define CONFIG_JFFS2_NAND
139/* nand device jffs2 lives on */
140#define CONFIG_JFFS2_DEV "nand0"
141/* start of jffs2 partition */
142#define CONFIG_JFFS2_PART_OFFSET 0x680000
143#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
144 /* partition */
145
146/* commands to include */
147#include <config_cmd_default.h>
148
149#define CONFIG_CMD_DHCP /* DHCP support */
150#define CONFIG_CMD_EXT2 /* EXT2 Support */
151#define CONFIG_CMD_FAT /* FAT support */
152#define CONFIG_CMD_I2C /* I2C serial bus support */
153#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
154#define CONFIG_CMD_MMC /* MMC support */
155#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
156#define CONFIG_CMD_NAND /* NAND support */
157#define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */
158
159#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
160#undef CONFIG_CMD_IMI /* iminfo */
161
162/* BOOTP/DHCP options */
163#define CONFIG_BOOTP_SUBNETMASK
164#define CONFIG_BOOTP_GATEWAY
165#define CONFIG_BOOTP_HOSTNAME
166#define CONFIG_BOOTP_NISDOMAIN
167#define CONFIG_BOOTP_BOOTPATH
168#define CONFIG_BOOTP_BOOTFILESIZE
169#define CONFIG_BOOTP_DNS
170#define CONFIG_BOOTP_DNS2
171#define CONFIG_BOOTP_SEND_HOSTNAME
172#define CONFIG_BOOTP_NTPSERVER
173#define CONFIG_BOOTP_TIMEOFFSET
174#undef CONFIG_BOOTP_VENDOREX
175
176/* Environment information */
177#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */
178
179#define CONFIG_BOOTDELAY 3
180
181#define CONFIG_EXTRA_ENV_SETTINGS \
182 "loadaddr=0x82000000\0" \
Thomas Weber2d76da22011-09-18 22:43:58 +0000183 "console=ttyO2,115200n8\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400184 "mmcdev=0\0" \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200185 "vram=12M\0" \
186 "dvimode=1024x768MR-16@60\0" \
187 "defaultdisplay=dvi\0" \
188 "nfsopts=hard,tcp,rsize=65536,wsize=65536\0" \
189 "kernelopts=rw\0" \
190 "commonargs=" \
191 "setenv bootargs console=${console} " \
192 "vram=${vram} " \
193 "omapfb.mode=dvi:${dvimode} " \
194 "omapdss.def_disp=${defaultdisplay}\0" \
195 "mmcargs=" \
196 "run commonargs; " \
197 "setenv bootargs ${bootargs} " \
198 "root=/dev/mmcblk0p2 " \
199 "${kernelopts}\0" \
200 "nandargs=" \
201 "run commonargs; " \
202 "setenv bootargs ${bootargs} " \
203 "omapfb.mode=dvi:${dvimode} " \
204 "omapdss.def_disp=${defaultdisplay} " \
205 "root=/dev/mtdblock4 " \
206 "rootfstype=jffs2 " \
207 "${kernelopts}\0" \
208 "netargs=" \
209 "run commonargs; " \
210 "setenv bootargs ${bootargs} " \
211 "root=/dev/nfs " \
212 "nfsroot=${serverip}:${rootpath},${nfsopts} " \
213 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off " \
214 "${kernelopts} " \
215 "dnsip1=${dnsip} " \
216 "dnsip2=${dnsip2}\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400217 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200218 "bootscript=echo Running bootscript from mmc ...; " \
219 "source ${loadaddr}\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400220 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200221 "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \
222 "mmcboot=echo Booting from mmc ...; " \
223 "run mmcargs; " \
224 "bootm ${loadaddr}\0" \
225 "nandboot=echo Booting from nand ...; " \
226 "run nandargs; " \
227 "nand read ${loadaddr} 280000 400000; " \
228 "bootm ${loadaddr}\0" \
229 "netboot=echo Booting from network ...; " \
230 "dhcp ${loadaddr}; " \
231 "run netargs; " \
232 "bootm ${loadaddr}\0" \
Tom Rinif4085012011-09-03 21:52:45 -0400233 "autoboot=if mmc rescan ${mmcdev}; then " \
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200234 "if run loadbootscript; then " \
235 "run bootscript; " \
236 "else " \
237 "if run loaduimage; then " \
238 "run mmcboot; " \
239 "else run nandboot; " \
240 "fi; " \
241 "fi; " \
242 "else run nandboot; fi\0"
243
244
245#define CONFIG_BOOTCOMMAND "run autoboot"
246
247/* Miscellaneous configurable options */
248#define CONFIG_SYS_LONGHELP /* undef to save memory */
249#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
250#define CONFIG_AUTO_COMPLETE 1
251#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
252#define CONFIG_SYS_PROMPT "OMAP3 DevKit8000 # "
253#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
254/* Print Buffer Size */
255#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
256 sizeof(CONFIG_SYS_PROMPT) + 16)
257#define CONFIG_SYS_MAXARGS 128 /* max number of command args */
258
259/* Boot Argument Buffer Size */
260#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
261
262#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000)
263#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
264 0x01000000) /* 16MB */
265
266#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000)
267
268/*
269 * OMAP3 has 12 GP timers, they can be driven by the system clock
270 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
271 * This rate is divided by a local divisor.
272 */
273#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
274#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
275#define CONFIG_SYS_HZ 1000
276
277/* The stack sizes are set up in start.S using the settings below */
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400278#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200279#ifdef CONFIG_USE_IRQ
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400280#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
281#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200282#endif
283
284/* Physical Memory Map */
285#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
286#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400287#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200288#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
289
290/* SDRAM Bank Allocation method */
291#define SDRC_R_B_C 1
292
293/* NAND and environment organization */
294#define PISMO1_NAND_SIZE GPMC_SIZE_128M
295
Sandeep Paulraj9c44ddc2009-09-09 11:50:40 -0400296#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200297
298#define CONFIG_ENV_IS_IN_NAND 1
299#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
300
Luca Ceresoli6cbec7b2011-04-20 11:02:05 -0400301#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200302
Thomas Weber66fca012010-10-18 15:38:15 +0200303#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Thomas Weber30f305c2010-11-18 08:45:25 +0100304#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
305#define CONFIG_SYS_INIT_RAM_SIZE 0x800
306#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
307 CONFIG_SYS_INIT_RAM_SIZE - \
308 GENERATED_GBL_DATA_SIZE)
Thomas Weber66fca012010-10-18 15:38:15 +0200309
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400310/* SRAM config */
311#define CONFIG_SYS_SRAM_START 0x40200000
312#define CONFIG_SYS_SRAM_SIZE 0x10000
313
314/* Defines for SPL */
315#define CONFIG_SPL
316#define CONFIG_SPL_NAND_SIMPLE
317
318#define CONFIG_SPL_LIBCOMMON_SUPPORT
319#define CONFIG_SPL_LIBDISK_SUPPORT
320#define CONFIG_SPL_I2C_SUPPORT
321#define CONFIG_SPL_LIBGENERIC_SUPPORT
322#define CONFIG_SPL_SERIAL_SUPPORT
323#define CONFIG_SPL_POWER_SUPPORT
324#define CONFIG_SPL_NAND_SUPPORT
Simon Schwarz99154712011-09-30 00:41:34 +0000325#define CONFIG_SPL_MMC_SUPPORT
326#define CONFIG_SPL_FAT_SUPPORT
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400327#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
Simon Schwarz99154712011-09-30 00:41:34 +0000328#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
329#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
330#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
Simon Schwarz3f6a4922011-09-14 15:32:17 -0400331
332#define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/
333#define CONFIG_SPL_MAX_SIZE 0xB400 /* 45 K */
334#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
335
336#define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/
337#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
338
339/* NAND boot config */
340#define CONFIG_SYS_NAND_PAGE_COUNT 64
341#define CONFIG_SYS_NAND_PAGE_SIZE 2048
342#define CONFIG_SYS_NAND_OOBSIZE 64
343#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
344#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
345#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
346 10, 11, 12, 13}
347
348#define CONFIG_SYS_NAND_ECCSIZE 512
349#define CONFIG_SYS_NAND_ECCBYTES 3
350
351#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
352 CONFIG_SYS_NAND_ECCSIZE)
353#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
354 CONFIG_SYS_NAND_ECCSTEPS)
355
356#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
357
358#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
359#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000
360
Tom Riniba75a812011-10-18 10:47:22 -0700361#define CONFIG_SYS_SPL_MALLOC_START 0x80108000
362#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */
363
Frederik Kriewitzc35d7cf2009-08-23 12:56:42 +0200364#endif /* __CONFIG_H */