Andre Przywara | 1ef9238 | 2013-09-19 18:06:42 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2013 |
| 3 | * Andre Przywara, Linaro |
| 4 | * |
| 5 | * Routines to transition ARMv7 processors from secure into non-secure state |
| 6 | * needed to enable ARMv7 virtualization for current hypervisors |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | #include <common.h> |
| 28 | #include <asm/armv7.h> |
| 29 | #include <asm/gic.h> |
| 30 | #include <asm/io.h> |
| 31 | |
| 32 | unsigned long gic_dist_addr; |
| 33 | |
| 34 | static unsigned int read_id_pfr1(void) |
| 35 | { |
| 36 | unsigned int reg; |
| 37 | |
| 38 | asm("mrc p15, 0, %0, c0, c1, 1\n" : "=r"(reg)); |
| 39 | return reg; |
| 40 | } |
| 41 | |
| 42 | static unsigned long get_gicd_base_address(void) |
| 43 | { |
| 44 | #ifdef CONFIG_ARM_GIC_BASE_ADDRESS |
| 45 | return CONFIG_ARM_GIC_BASE_ADDRESS + GIC_DIST_OFFSET; |
| 46 | #else |
| 47 | unsigned midr; |
| 48 | unsigned periphbase; |
| 49 | |
| 50 | /* check whether we are an Cortex-A15 or A7. |
| 51 | * The actual HYP switch should work with all CPUs supporting |
| 52 | * the virtualization extension, but we need the GIC address, |
| 53 | * which we know only for sure for those two CPUs. |
| 54 | */ |
| 55 | asm("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr)); |
| 56 | switch (midr & MIDR_PRIMARY_PART_MASK) { |
| 57 | case MIDR_CORTEX_A9_R0P1: |
| 58 | case MIDR_CORTEX_A15_R0P0: |
| 59 | case MIDR_CORTEX_A7_R0P0: |
| 60 | break; |
| 61 | default: |
| 62 | printf("nonsec: could not determine GIC address.\n"); |
| 63 | return -1; |
| 64 | } |
| 65 | |
| 66 | /* get the GIC base address from the CBAR register */ |
| 67 | asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase)); |
| 68 | |
| 69 | /* the PERIPHBASE can be mapped above 4 GB (lower 8 bits used to |
| 70 | * encode this). Bail out here since we cannot access this without |
| 71 | * enabling paging. |
| 72 | */ |
| 73 | if ((periphbase & 0xff) != 0) { |
| 74 | printf("nonsec: PERIPHBASE is above 4 GB, no access.\n"); |
| 75 | return -1; |
| 76 | } |
| 77 | |
| 78 | return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET; |
| 79 | #endif |
| 80 | } |
| 81 | |
Andre Przywara | ba6a169 | 2013-09-19 18:06:44 +0200 | [diff] [blame^] | 82 | static void kick_secondary_cpus_gic(unsigned long gicdaddr) |
| 83 | { |
| 84 | /* kick all CPUs (except this one) by writing to GICD_SGIR */ |
| 85 | writel(1U << 24, gicdaddr + GICD_SGIR); |
| 86 | } |
| 87 | |
| 88 | void __weak smp_kick_all_cpus(void) |
| 89 | { |
| 90 | kick_secondary_cpus_gic(gic_dist_addr); |
| 91 | } |
| 92 | |
Andre Przywara | 1ef9238 | 2013-09-19 18:06:42 +0200 | [diff] [blame] | 93 | int armv7_switch_nonsec(void) |
| 94 | { |
| 95 | unsigned int reg; |
| 96 | unsigned itlinesnr, i; |
| 97 | |
| 98 | /* check whether the CPU supports the security extensions */ |
| 99 | reg = read_id_pfr1(); |
| 100 | if ((reg & 0xF0) == 0) { |
| 101 | printf("nonsec: Security extensions not implemented.\n"); |
| 102 | return -1; |
| 103 | } |
| 104 | |
| 105 | /* the SCR register will be set directly in the monitor mode handler, |
| 106 | * according to the spec one should not tinker with it in secure state |
| 107 | * in SVC mode. Do not try to read it once in non-secure state, |
| 108 | * any access to it will trap. |
| 109 | */ |
| 110 | |
| 111 | gic_dist_addr = get_gicd_base_address(); |
| 112 | if (gic_dist_addr == -1) |
| 113 | return -1; |
| 114 | |
| 115 | /* enable the GIC distributor */ |
| 116 | writel(readl(gic_dist_addr + GICD_CTLR) | 0x03, |
| 117 | gic_dist_addr + GICD_CTLR); |
| 118 | |
| 119 | /* TYPER[4:0] contains an encoded number of available interrupts */ |
| 120 | itlinesnr = readl(gic_dist_addr + GICD_TYPER) & 0x1f; |
| 121 | |
| 122 | /* set all bits in the GIC group registers to one to allow access |
| 123 | * from non-secure state. The first 32 interrupts are private per |
| 124 | * CPU and will be set later when enabling the GIC for each core |
| 125 | */ |
| 126 | for (i = 1; i <= itlinesnr; i++) |
| 127 | writel((unsigned)-1, gic_dist_addr + GICD_IGROUPRn + 4 * i); |
| 128 | |
Andre Przywara | ba6a169 | 2013-09-19 18:06:44 +0200 | [diff] [blame^] | 129 | smp_set_core_boot_addr((unsigned long)_smp_pen, -1); |
| 130 | smp_kick_all_cpus(); |
| 131 | |
| 132 | /* call the non-sec switching code on this CPU also */ |
Andre Przywara | 1ef9238 | 2013-09-19 18:06:42 +0200 | [diff] [blame] | 133 | _nonsec_init(); |
| 134 | |
| 135 | return 0; |
| 136 | } |