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Marian Balakowicz991425f2006-03-14 16:24:38 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#include <common.h>
26#include <ioports.h>
27#include <mpc83xx.h>
28#include <asm/mpc8349_pci.h>
29#include <i2c.h>
Ben Warren80ddd222008-01-16 22:37:42 -050030#include <spi.h>
Marian Balakowicz991425f2006-03-14 16:24:38 +010031#include <miiphy.h>
Marian Balakowicz991425f2006-03-14 16:24:38 +010032#include <spd_sdram.h>
Jon Loeligera30a5492008-03-04 10:03:03 -060033
Kim Phillipsb3458d22007-12-20 15:57:28 -060034#if defined(CONFIG_OF_LIBFDT)
Kim Phillips3fde9e82007-08-15 22:30:33 -050035#include <libfdt.h>
Kim Phillipsbf0b5422006-11-01 00:10:40 -060036#endif
37
Marian Balakowicz991425f2006-03-14 16:24:38 +010038int fixed_sdram(void);
39void sdram_init(void);
40
41#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
42void ddr_enable_ecc(unsigned int dram_size);
43#endif
44
45int board_early_init_f (void)
46{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010048
49 /* Enable flash write */
50 bcsr[1] &= ~0x01;
51
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
Kumar Gala8fe9bf62006-04-20 13:45:32 -050053 /* Use USB PHY on SYS board */
54 bcsr[5] |= 0x02;
55#endif
56
Marian Balakowicz991425f2006-03-14 16:24:38 +010057 return 0;
58}
59
60#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
61
Becky Bruce9973e3c2008-06-09 16:03:40 -050062phys_size_t initdram (int board_type)
Marian Balakowicz991425f2006-03-14 16:24:38 +010063{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010065 u32 msize = 0;
66
67 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
68 return -1;
69
70 /* DDR SDRAM - Main SODIMM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
Marian Balakowicz991425f2006-03-14 16:24:38 +010072#if defined(CONFIG_SPD_EEPROM)
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +010073 msize = spd_sdram();
Marian Balakowicz991425f2006-03-14 16:24:38 +010074#else
75 msize = fixed_sdram();
76#endif
77 /*
78 * Initialize SDRAM if it is on local bus.
79 */
80 sdram_init();
81
82#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
83 /*
84 * Initialize and enable DDR ECC.
85 */
86 ddr_enable_ecc(msize * 1024 * 1024);
87#endif
Kim Phillipsbbea46f2007-08-16 22:52:48 -050088
Marian Balakowicz991425f2006-03-14 16:24:38 +010089 /* return total bus SDRAM size(bytes) -- DDR */
90 return (msize * 1024 * 1024);
91}
92
93#if !defined(CONFIG_SPD_EEPROM)
94/*************************************************************************
95 * fixed sdram init -- doesn't use serial presence detect.
96 ************************************************************************/
97int fixed_sdram(void)
98{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100100 u32 msize = 0;
101 u32 ddr_size;
102 u32 ddr_size_log2;
103
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104 msize = CONFIG_SYS_DDR_SIZE;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100105 for (ddr_size = msize << 20, ddr_size_log2 = 0;
106 (ddr_size > 1);
107 ddr_size = ddr_size>>1, ddr_size_log2++) {
108 if (ddr_size & 1) {
109 return -1;
110 }
111 }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100113 im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#if (CONFIG_SYS_DDR_SIZE != 256)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100116#warning Currenly any ddr size other than 256 is not supported
117#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +0800118#ifdef CONFIG_DDR_II
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119 im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
120 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
121 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
122 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
123 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
124 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
125 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
126 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
127 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
128 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
129 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
130 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800131#else
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100132 im->ddr.csbnds[2].csbnds = 0x0000000f;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100134
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200135 /* currently we use only one CS, so disable the other banks */
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100136 im->ddr.cs_config[0] = 0;
137 im->ddr.cs_config[1] = 0;
138 im->ddr.cs_config[3] = 0;
139
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
141 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200142
Marian Balakowicz991425f2006-03-14 16:24:38 +0100143 im->ddr.sdram_cfg =
144 SDRAM_CFG_SREN
145#if defined(CONFIG_DDR_2T_TIMING)
146 | SDRAM_CFG_2T_EN
147#endif
148 | 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100149#if defined (CONFIG_DDR_32BIT)
150 /* for 32-bit mode burst length is 8 */
151 im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
152#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800156#endif
Marian Balakowicz991425f2006-03-14 16:24:38 +0100157 udelay(200);
158
Rafal Jaworowskidc9e4992006-03-16 17:46:46 +0100159 /* enable DDR controller */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100160 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100161 return msize;
162}
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#endif/*!CONFIG_SYS_SPD_EEPROM*/
Marian Balakowicz991425f2006-03-14 16:24:38 +0100164
165
166int checkboard (void)
167{
Ira W. Snyder447ad572008-08-22 11:00:15 -0700168 /*
169 * Warning: do not read the BCSR registers here
170 *
171 * There is a timing bug in the 8349E and 8349EA BCSR code
172 * version 1.2 (read from BCSR 11) that will cause the CFI
173 * flash initialization code to overwrite BCSR 0, disabling
174 * the serial ports and gigabit ethernet
175 */
176
Marian Balakowicz991425f2006-03-14 16:24:38 +0100177 puts("Board: Freescale MPC8349EMDS\n");
178 return 0;
179}
180
Marian Balakowicz991425f2006-03-14 16:24:38 +0100181/*
182 * if MPC8349EMDS is soldered with SDRAM
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#if defined(CONFIG_SYS_BR2_PRELIM) \
185 && defined(CONFIG_SYS_OR2_PRELIM) \
186 && defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
187 && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
Marian Balakowicz991425f2006-03-14 16:24:38 +0100188/*
189 * Initialize SDRAM memory on the Local Bus.
190 */
191
192void sdram_init(void)
193{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
Haiying Wang4e190b02008-10-29 11:05:55 -0400195 volatile fsl_lbus_t *lbc = &immap->lbus;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100197
Marian Balakowicz991425f2006-03-14 16:24:38 +0100198 /*
199 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
200 */
201
202 /* setup mtrpt, lsrt and lbcr for LB bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
204 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
205 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100206 asm("sync");
207
208 /*
209 * Configure the SDRAM controller Machine Mode Register.
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100214 asm("sync");
215 *sdram_addr = 0xff;
216 udelay(100);
217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100219 asm("sync");
220 /*1 times*/
221 *sdram_addr = 0xff;
222 udelay(100);
223 /*2 times*/
224 *sdram_addr = 0xff;
225 udelay(100);
226 /*3 times*/
227 *sdram_addr = 0xff;
228 udelay(100);
229 /*4 times*/
230 *sdram_addr = 0xff;
231 udelay(100);
232 /*5 times*/
233 *sdram_addr = 0xff;
234 udelay(100);
235 /*6 times*/
236 *sdram_addr = 0xff;
237 udelay(100);
238 /*7 times*/
239 *sdram_addr = 0xff;
240 udelay(100);
241 /*8 times*/
242 *sdram_addr = 0xff;
243 udelay(100);
244
245 /* 0x58636733; mode register write operation */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
Marian Balakowicz991425f2006-03-14 16:24:38 +0100247 asm("sync");
248 *sdram_addr = 0xff;
249 udelay(100);
250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
Marian Balakowicz991425f2006-03-14 16:24:38 +0100252 asm("sync");
253 *sdram_addr = 0xff;
254 udelay(100);
255}
256#else
257void sdram_init(void)
258{
Marian Balakowicz991425f2006-03-14 16:24:38 +0100259}
260#endif
Marian Balakowiczd326f4a2006-03-16 15:19:35 +0100261
Ben Warren80ddd222008-01-16 22:37:42 -0500262/*
263 * The following are used to control the SPI chip selects for the SPI command.
264 */
Ben Warrenf8cc3122008-06-08 23:28:33 -0700265#ifdef CONFIG_MPC8XXX_SPI
Ben Warren80ddd222008-01-16 22:37:42 -0500266
267#define SPI_CS_MASK 0x80000000
268
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200269int spi_cs_is_valid(unsigned int bus, unsigned int cs)
270{
271 return bus == 0 && cs == 0;
272}
273
274void spi_cs_activate(struct spi_slave *slave)
Ben Warren80ddd222008-01-16 22:37:42 -0500275{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
Ben Warren80ddd222008-01-16 22:37:42 -0500277
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200278 iopd->dat &= ~SPI_CS_MASK;
Ben Warren80ddd222008-01-16 22:37:42 -0500279}
280
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200281void spi_cs_deactivate(struct spi_slave *slave)
282{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283 volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
Ben Warren80ddd222008-01-16 22:37:42 -0500284
Haavard Skinnemoend255bb02008-05-16 11:10:31 +0200285 iopd->dat |= SPI_CS_MASK;
286}
Ben Warren80ddd222008-01-16 22:37:42 -0500287#endif /* CONFIG_HARD_SPI */
288
Kim Phillips3fde9e82007-08-15 22:30:33 -0500289#if defined(CONFIG_OF_BOARD_SETUP)
290void ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600291{
Kim Phillips3fde9e82007-08-15 22:30:33 -0500292 ft_cpu_setup(blob, bd);
293#ifdef CONFIG_PCI
294 ft_pci_setup(blob, bd);
295#endif
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600296}
297#endif