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Dirk Behme2be2c6c2009-01-28 21:39:58 +01001/*
2 * (C) Copyright 2008
3 * Grazvydas Ignotas <notasas@gmail.com>
4 *
5 * Derived from Beagle Board, 3430 SDP, and OMAP3EVM code by
6 * Richard Woodruff <r-woodruff2@ti.com>
7 * Syed Mohammed Khasim <khasim@ti.com>
8 * Sunil Kumar <sunilsaini05@gmail.com>
9 * Shashi Ranjan <shashiranjanmca05@gmail.com>
10 *
11 * (C) Copyright 2004-2008
12 * Texas Instruments, <www.ti.com>
13 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Dirk Behme2be2c6c2009-01-28 21:39:58 +010015 */
16#include <common.h>
Tom Rix2c155132009-06-28 12:52:30 -050017#include <twl4030.h>
Dirk Behme2be2c6c2009-01-28 21:39:58 +010018#include <asm/io.h>
Grazvydas Ignotas7cad4462012-03-22 13:49:22 +000019#include <asm/gpio.h>
Tom Rini86c5c542011-09-03 21:51:25 -040020#include <asm/arch/mmc_host_def.h>
Dirk Behme2be2c6c2009-01-28 21:39:58 +010021#include <asm/arch/mux.h>
Aneesh V080a46e2011-07-31 20:30:53 +000022#include <asm/arch/gpio.h>
Dirk Behme2be2c6c2009-01-28 21:39:58 +010023#include <asm/arch/sys_proto.h>
24#include <asm/mach-types.h>
25#include "pandora.h"
26
John Rigby29565322010-12-20 18:27:51 -070027DECLARE_GLOBAL_DATA_PTR;
28
Grazvydas Ignotas5246d012010-06-08 17:19:22 -040029#define TWL4030_BB_CFG_BBCHEN (1 << 4)
30#define TWL4030_BB_CFG_BBSEL_3200MV (3 << 2)
31#define TWL4030_BB_CFG_BBISEL_500UA 2
32
Grazvydas Ignotas7cad4462012-03-22 13:49:22 +000033#define CONTROL_WKUP_CTRL 0x48002a5c
34#define GPIO_IO_PWRDNZ (1 << 6)
35#define PBIASLITEVMODE1 (1 << 8)
36
Tom Rix58911512009-04-01 22:02:20 -050037/*
Dirk Behme2be2c6c2009-01-28 21:39:58 +010038 * Routine: board_init
39 * Description: Early hardware init.
Tom Rix58911512009-04-01 22:02:20 -050040 */
Dirk Behme2be2c6c2009-01-28 21:39:58 +010041int board_init(void)
42{
Dirk Behme2be2c6c2009-01-28 21:39:58 +010043 gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
44 /* board id for Linux */
45 gd->bd->bi_arch_number = MACH_TYPE_OMAP3_PANDORA;
46 /* boot param addr */
47 gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
48
49 return 0;
50}
51
Grazvydas Ignotas7cad4462012-03-22 13:49:22 +000052static void set_output_gpio(unsigned int gpio, int value)
53{
54 int ret;
55
56 ret = gpio_request(gpio, "");
57 if (ret != 0) {
58 printf("could not request GPIO %u\n", gpio);
59 return;
60 }
61 ret = gpio_direction_output(gpio, value);
62 if (ret != 0)
63 printf("could not set GPIO %u to %d\n", gpio, value);
64}
65
Tom Rix58911512009-04-01 22:02:20 -050066/*
Dirk Behme2be2c6c2009-01-28 21:39:58 +010067 * Routine: misc_init_r
68 * Description: Configure board specific parts
Tom Rix58911512009-04-01 22:02:20 -050069 */
Dirk Behme2be2c6c2009-01-28 21:39:58 +010070int misc_init_r(void)
71{
Grazvydas Ignotas7cad4462012-03-22 13:49:22 +000072 t2_t *t2_base = (t2_t *)T2_BASE;
73 u32 pbias_lite;
Dirk Behme2be2c6c2009-01-28 21:39:58 +010074
Grazvydas Ignotasead39d72009-12-10 17:10:21 +020075 twl4030_led_init(TWL4030_LED_LEDEN_LEDBON);
Dirk Behme2be2c6c2009-01-28 21:39:58 +010076
Grazvydas Ignotas7cad4462012-03-22 13:49:22 +000077 /* set up dual-voltage GPIOs to 1.8V */
78 pbias_lite = readl(&t2_base->pbias_lite);
79 pbias_lite &= ~PBIASLITEVMODE1;
80 pbias_lite |= PBIASLITEPWRDNZ1;
81 writel(pbias_lite, &t2_base->pbias_lite);
82 if (get_cpu_family() == CPU_OMAP36XX)
83 writel(readl(CONTROL_WKUP_CTRL) | GPIO_IO_PWRDNZ,
84 CONTROL_WKUP_CTRL);
Dirk Behme2be2c6c2009-01-28 21:39:58 +010085
Grazvydas Ignotas7cad4462012-03-22 13:49:22 +000086 /* make sure audio and BT chips are in powerdown state */
87 set_output_gpio(14, 0);
88 set_output_gpio(15, 0);
89 set_output_gpio(118, 0);
90
91 /* enable USB supply */
92 set_output_gpio(164, 1);
93
94 /* wifi needs a short pulse to enter powersave state */
95 set_output_gpio(23, 1);
96 udelay(5000);
97 gpio_direction_output(23, 0);
Dirk Behme2be2c6c2009-01-28 21:39:58 +010098
Grazvydas Ignotas5246d012010-06-08 17:19:22 -040099 /* Enable battery backup capacitor (3.2V, 0.5mA charge current) */
100 twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER,
Nishanth Menon0208aaf2013-03-26 05:20:49 +0000101 TWL4030_PM_RECEIVER_BB_CFG,
Grazvydas Ignotas5246d012010-06-08 17:19:22 -0400102 TWL4030_BB_CFG_BBCHEN | TWL4030_BB_CFG_BBSEL_3200MV |
Nishanth Menon0208aaf2013-03-26 05:20:49 +0000103 TWL4030_BB_CFG_BBISEL_500UA);
Grazvydas Ignotas5246d012010-06-08 17:19:22 -0400104
Dirk Behmee6a6a702009-03-12 19:30:50 +0100105 dieid_num_r();
106
Dirk Behme2be2c6c2009-01-28 21:39:58 +0100107 return 0;
108}
109
Tom Rix58911512009-04-01 22:02:20 -0500110/*
Dirk Behme2be2c6c2009-01-28 21:39:58 +0100111 * Routine: set_muxconf_regs
112 * Description: Setting up the configuration Mux registers specific to the
113 * hardware. Many pins need to be moved from protect to primary
114 * mode.
Tom Rix58911512009-04-01 22:02:20 -0500115 */
Dirk Behme2be2c6c2009-01-28 21:39:58 +0100116void set_muxconf_regs(void)
117{
118 MUX_PANDORA();
Grazvydas Ignotas10cd73b2012-03-22 13:49:21 +0000119 if (get_cpu_family() == CPU_OMAP36XX) {
120 MUX_PANDORA_3730();
121 }
Dirk Behme2be2c6c2009-01-28 21:39:58 +0100122}
Tom Rini86c5c542011-09-03 21:51:25 -0400123
124#ifdef CONFIG_GENERIC_MMC
125int board_mmc_init(bd_t *bis)
126{
Nikita Kiryanove3913f52012-12-03 02:19:47 +0000127 return omap_mmc_init(0, 0, 0, -1, -1);
Tom Rini86c5c542011-09-03 21:51:25 -0400128}
129#endif