| Wolfgang Denk | 46263f2 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 1 | /* |
| Wolfgang Denk | 1b387ef | 2013-09-17 11:24:06 +0200 | [diff] [blame] | 2 | * SPDX-License-Identifier: GPL-2.0 IBM-pibs |
| Wolfgang Denk | 46263f2 | 2013-07-28 22:12:45 +0200 | [diff] [blame] | 3 | */ |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 4 | /*------------------------------------------------------------------------- */ |
| 5 | /* Function: ext_bus_cntlr_init */ |
| 6 | /* Description: Initializes the External Bus Controller for the external */ |
| 7 | /* peripherals. IMPORTANT: For pass1 this code must run from */ |
| 8 | /* cache since you can not reliably change a peripheral banks */ |
| 9 | /* timing register (pbxap) while running code from that bank. */ |
| 10 | /* For ex., since we are running from ROM on bank 0, we can NOT */ |
| 11 | /* execute the code that modifies bank 0 timings from ROM, so */ |
| 12 | /* we run it from cache. */ |
| 13 | /* */ |
| 14 | /* */ |
| 15 | /* The layout for the PEI JSE board: */ |
| 16 | /* Bank 0 - Flash and SRAM */ |
| 17 | /* Bank 1 - SystemACE */ |
| 18 | /* Bank 2 - not used */ |
| 19 | /* Bank 3 - not used */ |
| 20 | /* Bank 4 - not used */ |
| 21 | /* Bank 5 - not used */ |
| 22 | /* Bank 6 - not used */ |
| 23 | /* Bank 7 - not used */ |
| 24 | /*------------------------------------------------------------------------- */ |
| Stefan Roese | b36df56 | 2010-09-09 19:18:00 +0200 | [diff] [blame] | 25 | #include <asm/ppc4xx.h> |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 26 | |
| 27 | #include <ppc_asm.tmpl> |
| 28 | #include <ppc_defs.h> |
| 29 | |
| 30 | #include <asm/cache.h> |
| 31 | #include <asm/mmu.h> |
| 32 | |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 33 | .globl ext_bus_cntlr_init |
| 34 | ext_bus_cntlr_init: |
| 35 | mflr r4 /* save link register */ |
| 36 | bl ..getAddr |
| 37 | ..getAddr: |
| 38 | mflr r3 /* get address of ..getAddr */ |
| 39 | mtlr r4 /* restore link register */ |
| 40 | addi r4,0,14 /* set ctr to 10; used to prefetch */ |
| 41 | mtctr r4 /* 10 cache lines to fit this function */ |
| 42 | /* in cache (gives us 8x10=80 instrctns) */ |
| 43 | ..ebcloop: |
| 44 | icbt r0,r3 /* prefetch cache line for addr in r3 */ |
| 45 | addi r3,r3,32 /* move to next cache line */ |
| 46 | bdnz ..ebcloop /* continue for 10 cache lines */ |
| 47 | |
| 48 | /*----------------------------------------------------------------- */ |
| 49 | /* Delay to ensure all accesses to ROM are complete before changing */ |
| 50 | /* bank 0 timings. 200usec should be enough. */ |
| 51 | /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ |
| 52 | /*----------------------------------------------------------------- */ |
| 53 | addis r3,0,0x0 |
| 54 | ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ |
| 55 | mtctr r3 |
| 56 | ..spinlp: |
| 57 | bdnz ..spinlp /* spin loop */ |
| 58 | |
| 59 | /*----------------------------------------------------------------- */ |
| 60 | /* Memory Bank 0 (Flash) initialization */ |
| 61 | /*----------------------------------------------------------------- */ |
| 62 | |
| Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 63 | addi r4,0,PB1AP |
| 64 | mtdcr EBC0_CFGADDR,r4 |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 65 | addis r4,0,0x9B01 |
| 66 | ori r4,r4,0x5480 |
| Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 67 | mtdcr EBC0_CFGDATA,r4 |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 68 | |
| Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 69 | addi r4,0,PB0CR |
| 70 | mtdcr EBC0_CFGADDR,r4 |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 71 | addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ |
| 72 | ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ |
| Stefan Roese | d1c3b27 | 2009-09-09 16:25:29 +0200 | [diff] [blame] | 73 | mtdcr EBC0_CFGDATA,r4 |
| wdenk | db01a2e | 2004-04-15 23:14:49 +0000 | [diff] [blame] | 74 | |
| 75 | blr |