blob: 93c7f4b8c9b111f139c53b6920440a8de098bbfb [file] [log] [blame]
Kumar Gala1167a2f2008-08-26 08:02:30 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Kumar Gala1167a2f2008-08-26 08:02:30 -05005 */
6
7#include <common.h>
Kumar Gala1167a2f2008-08-26 08:02:30 -05008
York Sun5614e712013-09-30 09:22:09 -07009#include <fsl_ddr_sdram.h>
10#include <fsl_ddr_dimm_params.h>
Kumar Gala1167a2f2008-08-26 08:02:30 -050011
Haiying Wangdfb49102008-10-03 12:36:55 -040012void fsl_ddr_board_options(memctl_options_t *popts,
13 dimm_params_t *pdimm,
14 unsigned int ctrl_num)
Kumar Gala1167a2f2008-08-26 08:02:30 -050015{
16 /*
17 * Factors to consider for clock adjust:
18 * - number of chips on bus
19 * - position of slot
20 * - DDR1 vs. DDR2?
21 * - ???
22 *
23 * This needs to be determined on a board-by-board basis.
24 * 0110 3/4 cycle late
25 * 0111 7/8 cycle late
26 */
27 popts->clk_adjust = 7;
28
29 /*
30 * Factors to consider for CPO:
31 * - frequency
32 * - ddr1 vs. ddr2
33 */
34 popts->cpo_override = 10;
35
36 /*
37 * Factors to consider for write data delay:
38 * - number of DIMMs
39 *
40 * 1 = 1/4 clock delay
41 * 2 = 1/2 clock delay
42 * 3 = 3/4 clock delay
43 * 4 = 1 clock delay
44 * 5 = 5/4 clock delay
45 * 6 = 3/2 clock delay
46 */
47 popts->write_data_delay = 3;
48
Dave Liub4983e12008-11-21 16:31:43 +080049 /* 2T timing enable */
Priyanka Jain0dd38a32013-09-25 10:41:19 +053050 popts->twot_en = 1;
Dave Liub4983e12008-11-21 16:31:43 +080051
Kumar Gala1167a2f2008-08-26 08:02:30 -050052 /*
53 * Factors to consider for half-strength driver enable:
54 * - number of DIMMs installed
55 */
56 popts->half_strength_driver_enable = 0;
57}