blob: 4a4ddeb91fffdcf086ce9b0f25d1bc69400ccb33 [file] [log] [blame]
Tom Rixcd782632009-06-28 12:52:29 -05001/*
2 * Copyright (c) 2009 Wind River Systems, Inc.
3 * Tom Rix <Tom.Rix at windriver.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
Tom Rix2c155132009-06-28 12:52:30 -050020 * twl4030_power_reset_init is derived from code on omapzoom,
21 * git://git.omapzoom.com/repo/u-boot.git
Tom Rixcd782632009-06-28 12:52:29 -050022 *
23 * Copyright (C) 2007-2009 Texas Instruments, Inc.
Tom Rix2c155132009-06-28 12:52:30 -050024 *
25 * twl4030_power_init is from cpu/omap3/common.c, power_init_r
26 *
27 * (C) Copyright 2004-2008
28 * Texas Instruments, <www.ti.com>
29 *
30 * Author :
31 * Sunil Kumar <sunilsaini05 at gmail.com>
32 * Shashi Ranjan <shashiranjanmca05 at gmail.com>
33 *
34 * Derived from Beagle Board and 3430 SDP code by
35 * Richard Woodruff <r-woodruff2 at ti.com>
36 * Syed Mohammed Khasim <khasim at ti.com>
37 *
Tom Rixcd782632009-06-28 12:52:29 -050038 */
39
40#include <twl4030.h>
41
42/*
43 * Power Reset
44 */
45void twl4030_power_reset_init(void)
46{
47 u8 val = 0;
48 if (twl4030_i2c_read_u8(TWL4030_CHIP_PM_MASTER, &val,
49 TWL4030_PM_MASTER_P1_SW_EVENTS)) {
50 printf("Error:TWL4030: failed to read the power register\n");
51 printf("Could not initialize hardware reset\n");
52 } else {
53 val |= TWL4030_PM_MASTER_SW_EVENTS_STOPON_PWRON;
54 if (twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, val,
55 TWL4030_PM_MASTER_P1_SW_EVENTS)) {
56 printf("Error:TWL4030: failed to write the power register\n");
57 printf("Could not initialize hardware reset\n");
58 }
59 }
60}
61
Tom Rix2c155132009-06-28 12:52:30 -050062/*
Steve Sakoman5a0a82f2010-08-10 12:58:39 -070063 * Set Device Group and Voltage
Tom Rix2c155132009-06-28 12:52:30 -050064 */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -070065void twl4030_pmrecv_vsel_cfg(u8 vsel_reg, u8 vsel_val,
66 u8 dev_grp, u8 dev_grp_sel)
67{
68 /* Select the Device Group */
69 twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, dev_grp_sel,
70 dev_grp);
71
72 /* Select the Voltage */
73 twl4030_i2c_write_u8(TWL4030_CHIP_PM_RECEIVER, vsel_val,
74 vsel_reg);
75}
Tom Rix2c155132009-06-28 12:52:30 -050076
77void twl4030_power_init(void)
78{
Tom Rix2c155132009-06-28 12:52:30 -050079 /* set VAUX3 to 2.8V */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -070080 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX3_DEDICATED,
81 TWL4030_PM_RECEIVER_VAUX3_VSEL_28,
82 TWL4030_PM_RECEIVER_VAUX3_DEV_GRP,
83 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix2c155132009-06-28 12:52:30 -050084
85 /* set VPLL2 to 1.8V */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -070086 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VPLL2_DEDICATED,
87 TWL4030_PM_RECEIVER_VPLL2_VSEL_18,
88 TWL4030_PM_RECEIVER_VPLL2_DEV_GRP,
89 TWL4030_PM_RECEIVER_DEV_GRP_ALL);
Tom Rix2c155132009-06-28 12:52:30 -050090
91 /* set VDAC to 1.8V */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -070092 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VDAC_DEDICATED,
93 TWL4030_PM_RECEIVER_VDAC_VSEL_18,
94 TWL4030_PM_RECEIVER_VDAC_DEV_GRP,
95 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rix2c155132009-06-28 12:52:30 -050096}
97
Tom Rixfccc0fc2009-06-28 12:52:31 -050098void twl4030_power_mmc_init(void)
99{
Ash Charles528cdca2011-09-28 06:47:16 +0000100 /* Set VMMC1 to 3.15 Volts */
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700101 twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC1_DEDICATED,
Ash Charles528cdca2011-09-28 06:47:16 +0000102 TWL4030_PM_RECEIVER_VMMC1_VSEL_32,
Steve Sakoman5a0a82f2010-08-10 12:58:39 -0700103 TWL4030_PM_RECEIVER_VMMC1_DEV_GRP,
104 TWL4030_PM_RECEIVER_DEV_GRP_P1);
Tom Rixfccc0fc2009-06-28 12:52:31 -0500105}