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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * Workaround for layout bug on prototype board
33 */
34#define PCU_E_WITH_SWAPPED_CS 1
35
36/*
37 * High Level Configuration Options
38 * (easy to change)
39 */
40
41#define CONFIG_MPC860 1 /* This is a MPC860T CPU */
42#define CONFIG_MPC860T 1
43#define CONFIG_PCU_E 1 /* ...on a PCU E board */
44
45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
46
47#define CONFIG_BAUDRATE 9600
48#if 0
49#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
50#else
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52#endif
53
54#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
55
56#undef CONFIG_BOOTARGS
57#define CONFIG_BOOTCOMMAND \
58 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010059 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenk0f8c9762002-08-19 11:57:05 +000061 "bootm"
62
63#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
64#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
65
66#undef CONFIG_WATCHDOG /* watchdog disabled */
67
68#define CONFIG_STATUS_LED 1 /* Status LED enabled */
69
70#define CONFIG_PRAM 2048 /* reserve 2 MB "protected RAM" */
71
72#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
73
74#define CONFIG_SPI /* enable SPI driver */
75#define CONFIG_SPI_X /* 16 bit EEPROM addressing */
76
77#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
78#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
79#define CFG_I2C_SLAVE 0x7F
80
81
82/* ----------------------------------------------------------------
83 * Offset to initial SPI buffers in DPRAM (used if the environment
84 * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
85 * use at an early stage. It is used between the two initialization
86 * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
87 * far enough from the start of the data area (as well as from the
88 * stack pointer).
89 * ---------------------------------------------------------------- */
90#define CFG_SPI_INIT_OFFSET 0xB00
91
92#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk414eec32005-04-02 22:37:54 +000093 CFG_CMD_BSP | \
wdenk0f8c9762002-08-19 11:57:05 +000094 CFG_CMD_DATE | \
wdenk414eec32005-04-02 22:37:54 +000095 CFG_CMD_DHCP | \
wdenk0f8c9762002-08-19 11:57:05 +000096 CFG_CMD_EEPROM | \
wdenk414eec32005-04-02 22:37:54 +000097 CFG_CMD_NFS | \
98 CFG_CMD_SNTP )
wdenk0f8c9762002-08-19 11:57:05 +000099
100#define CONFIG_BOOTP_MASK \
101 ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
102
103/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
104#include <cmd_confdefs.h>
105
106/*----------------------------------------------------------------------*/
107
108/*
109 * Miscellaneous configurable options
110 */
111#define CFG_LONGHELP /* undef to save memory */
112#define CFG_PROMPT "=> " /* Monitor Command Prompt */
113#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
114#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
115#else
116#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
117#endif
118#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
119#define CFG_MAXARGS 16 /* max number of command args */
120#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
121
122#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
123#define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
124
125#define CFG_LOAD_ADDR 0x00100000 /* default load address */
126
127#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
128
129/* Ethernet hardware configuration done using port pins */
130#define CFG_PB_ETH_RESET 0x00000020 /* PB 26 */
131#if PCU_E_WITH_SWAPPED_CS /* XXX */
132#define CFG_PA_ETH_MDDIS 0x4000 /* PA 1 */
133#define CFG_PB_ETH_POWERDOWN 0x00000800 /* PB 20 */
134#define CFG_PB_ETH_CFG1 0x00000400 /* PB 21 */
135#define CFG_PB_ETH_CFG2 0x00000200 /* PB 22 */
136#define CFG_PB_ETH_CFG3 0x00000100 /* PB 23 */
137#else /* XXX */
138#define CFG_PB_ETH_MDDIS 0x00000010 /* PB 27 */
139#define CFG_PB_ETH_POWERDOWN 0x00000100 /* PB 23 */
140#define CFG_PB_ETH_CFG1 0x00000200 /* PB 22 */
141#define CFG_PB_ETH_CFG2 0x00000400 /* PB 21 */
142#define CFG_PB_ETH_CFG3 0x00000800 /* PB 20 */
143#endif /* XXX */
144
145/* Ethernet settings:
146 * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
147 */
148#define CFG_ETH_MDDIS_VALUE 0
149#define CFG_ETH_CFG1_VALUE 1
150#define CFG_ETH_CFG2_VALUE 1
151#define CFG_ETH_CFG3_VALUE 1
152
153/* PUMA configuration */
154#if PCU_E_WITH_SWAPPED_CS /* XXX */
155#define CFG_PB_PUMA_PROG 0x00000010 /* PB 27 */
156#else /* XXX */
157#define CFG_PA_PUMA_PROG 0x4000 /* PA 1 */
158#endif /* XXX */
159#define CFG_PC_PUMA_DONE 0x0008 /* PC 12 */
160#define CFG_PC_PUMA_INIT 0x0004 /* PC 13 */
161
162#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
163
164#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
165
166/*
167 * Low Level Configuration Settings
168 * (address mappings, register initial values, etc.)
169 * You should know what you are doing if you make changes here.
170 */
171/*-----------------------------------------------------------------------
172 * Internal Memory Mapped Register
173 */
174#define CFG_IMMR 0xFE000000
175
176/*-----------------------------------------------------------------------
177 * Definitions for initial stack pointer and data area (in DPRAM)
178 */
179#define CFG_INIT_RAM_ADDR CFG_IMMR
180#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
181#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
182#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
183#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
184
185/*-----------------------------------------------------------------------
186 * Address accessed to reset the board - must not be mapped/assigned
187 */
188#define CFG_RESET_ADDRESS 0xFEFFFFFF
189
190/*-----------------------------------------------------------------------
191 * Start addresses for the final memory configuration
192 * (Set up by the startup code)
193 * Please note that CFG_SDRAM_BASE _must_ start at 0
194 */
195#define CFG_SDRAM_BASE 0x00000000
196/* this is an ugly hack needed because of the silly non-constant address map */
197#define CFG_FLASH_BASE (0-flash_info[0].size-flash_info[1].size)
198
199#if defined(DEBUG)
200#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
201#else
202#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
203#endif
204#define CFG_MONITOR_BASE TEXT_BASE
205#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
206
207/*
208 * For booting Linux, the board info and command line data
209 * have to be in the first 8 MB of memory, since this is
210 * the maximum mapped by the Linux kernel during initialization.
211 */
212#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
213/*-----------------------------------------------------------------------
214 * FLASH organization
215 */
216#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
217#define CFG_MAX_FLASH_SECT 160 /* max number of sectors on one chip */
218
219#define CFG_FLASH_ERASE_TOUT 180000 /* Timeout for Flash Erase (in ms) */
220#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
221
222#if 0
223/* Start port with environment in flash; switch to SPI EEPROM later */
224#define CFG_ENV_IS_IN_FLASH 1
225#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment */
226#define CFG_ENV_ADDR 0xFFFFE000 /* Address of Environment Sector */
227#define CFG_ENV_SECT_SIZE 0x2000 /* use the top-most 8k boot sector */
wdenk7e780362004-04-08 22:31:29 +0000228#define CFG_ENV_IS_EMBEDDED 1 /* short-cut compile-time test */
wdenk0f8c9762002-08-19 11:57:05 +0000229#else
230/* Final version: environment in EEPROM */
231#define CFG_ENV_IS_IN_EEPROM 1
232#define CFG_I2C_EEPROM_ADDR 0
233#define CFG_I2C_EEPROM_ADDR_LEN 2
234#define CFG_ENV_OFFSET 1024
235#define CFG_ENV_SIZE 1024
236#endif
237
238/*-----------------------------------------------------------------------
239 * Cache Configuration
240 */
241#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
242#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
243
244/*-----------------------------------------------------------------------
245 * SYPCR - System Protection Control 11-9
246 * SYPCR can only be written once after reset!
247 *-----------------------------------------------------------------------
248 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
249 */
250#if defined(CONFIG_WATCHDOG)
251#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
252 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
253#else
254#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
255#endif
256
257/*-----------------------------------------------------------------------
258 * SIUMCR - SIU Module Configuration 11-6
259 *-----------------------------------------------------------------------
260 * External Arbitration max. priority (7),
261 * Debug pins configuration '11',
262 * Asynchronous external master enable.
263 */
264/* => 0x70600200 */
265#define CFG_SIUMCR (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
266
267/*-----------------------------------------------------------------------
268 * TBSCR - Time Base Status and Control 11-26
269 *-----------------------------------------------------------------------
270 * Clear Reference Interrupt Status, Timebase freezing enabled
271 */
272#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
273
274/*-----------------------------------------------------------------------
275 * PISCR - Periodic Interrupt Status and Control 11-31
276 *-----------------------------------------------------------------------
277 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
278 */
279#define CFG_PISCR (PISCR_PS | PISCR_PITF)
280
281/*-----------------------------------------------------------------------
282 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
283 *-----------------------------------------------------------------------
284 * Reset PLL lock status sticky bit, timer expired status bit and timer
285 * interrupt status bit, set PLL multiplication factor !
286 */
287/* 0x00004080 */
288#define CFG_PLPRCR_MF 0 /* (0+1) * 50 = 50 MHz Clock */
289#define CFG_PLPRCR \
290 ( (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) | \
291 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \
292 /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
293 PLPRCR_CSR /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/ \
294 )
295
296#define CONFIG_8xx_GCLK_FREQ ((CFG_PLPRCR_MF+1)*50000000)
297
298/*-----------------------------------------------------------------------
299 * SCCR - System Clock and reset Control Register 15-27
300 *-----------------------------------------------------------------------
301 * Set clock output, timebase and RTC source and divider,
302 * power management and some other internal clocks
303 *
304 * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
305 */
306#define SCCR_MASK SCCR_EBDF11
307/* 0x01800000 */
308#define CFG_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
309 SCCR_RTDIV | SCCR_RTSEL | \
310 /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
311 SCCR_EBDF00 | SCCR_DFSYNC00 | \
312 SCCR_DFBRG00 | SCCR_DFNL000 | \
313 SCCR_DFNH000 | SCCR_DFLCD100 | \
314 SCCR_DFALCD01)
315
316/*-----------------------------------------------------------------------
317 * RTCSC - Real-Time Clock Status and Control Register 11-27
318 *-----------------------------------------------------------------------
319 *
320 * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
321 *
322 * Don't expect the "date" command to work without a 32kHz clock input!
323 */
324/* 0x00C3 => 0x0003 */
325#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
326
327
328/*-----------------------------------------------------------------------
329 * RCCR - RISC Controller Configuration Register 19-4
330 *-----------------------------------------------------------------------
331 */
332#define CFG_RCCR 0x0000
333
334/*-----------------------------------------------------------------------
335 * RMDS - RISC Microcode Development Support Control Register
336 *-----------------------------------------------------------------------
337 */
338#define CFG_RMDS 0
339
340/*-----------------------------------------------------------------------
341 *
342 * Interrupt Levels
343 *-----------------------------------------------------------------------
344 */
345#define CFG_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
346
347/*-----------------------------------------------------------------------
348 *
349 *-----------------------------------------------------------------------
350 *
351 */
352#define CFG_DER 0
353
354/*
355 * Init Memory Controller:
356 *
357 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
358 */
359
360#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */
361#if PCU_E_WITH_SWAPPED_CS /* XXX */
362#define FLASH_BASE6_PRELIM 0xFF000000 /* FLASH bank #1 */
363#else /* XXX */
364#define FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank #1 */
365#endif /* XXX */
366
367/*
368 * used to re-map FLASH: restrict access enough but not too much to
369 * meddle with FLASH accesses
370 */
371#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
372#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
373
374/* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1 */
375#define CFG_OR_TIMING_FLASH (OR_SCY_8_CLK | OR_EHTR)
376
377#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
378 CFG_OR_TIMING_FLASH)
379#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
380 CFG_OR_TIMING_FLASH)
381/* 16 bit, bank valid */
382#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
383
384#if PCU_E_WITH_SWAPPED_CS /* XXX */
385#define CFG_OR6_REMAP CFG_OR0_REMAP
386#define CFG_OR6_PRELIM CFG_OR0_PRELIM
387#define CFG_BR6_PRELIM ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
388#else /* XXX */
389#define CFG_OR1_REMAP CFG_OR0_REMAP
390#define CFG_OR1_PRELIM CFG_OR0_PRELIM
391#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
392#endif /* XXX */
393
394/*
395 * BR2/OR2: SDRAM
396 *
397 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
398 */
399#if PCU_E_WITH_SWAPPED_CS /* XXX */
400#define SDRAM_BASE5_PRELIM 0x00000000 /* SDRAM bank */
401#else /* XXX */
402#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank */
403#endif /* XXX */
404#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map 128 MB (>SDRAM_MAX_SIZE!) */
405#define SDRAM_TIMING OR_CSNT_SAM /* SDRAM-Timing */
406
407#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
408
409#if PCU_E_WITH_SWAPPED_CS /* XXX */
410#define CFG_OR5_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
411#define CFG_BR5_PRELIM ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
412#else /* XXX */
413#define CFG_OR2_PRELIM (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
414#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
415#endif /* XXX */
416
417/*
418 * BR3/OR3: CAN Controller
419 * BR3: 0x10000401 OR3: 0xffff818a
420 */
421#define CAN_CTRLR_BASE 0x10000000 /* CAN Controller */
422#define CAN_CTRLR_OR_AM 0xFFFF8000 /* 32 kB */
423#define CAN_CTRLR_TIMING (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
424
425#if PCU_E_WITH_SWAPPED_CS /* XXX */
426#define CFG_BR4_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
427#define CFG_OR4_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
428#else /* XXX */
429#define CFG_BR3_PRELIM ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
430#define CFG_OR3_PRELIM (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
431#endif /* XXX */
432
433/*
434 * BR4/OR4: PUMA Config
435 *
436 * Memory controller will be used in 2 modes:
437 *
438 * - "read" mode:
439 * BR4: 0x10100801 OR4: 0xffff8530
440 * - "load" mode (chip select on UPM B):
441 * BR4: 0x101008c1 OR4: 0xffff8630
442 *
443 * Default initialization is in "read" mode
444 */
445#define PUMA_CONF_BASE 0x10100000 /* PUMA Config */
446#define PUMA_CONF_OR_AM 0xFFFF8000 /* 32 kB */
447#define PUMA_CONF_LOAD_TIMING (OR_ACS_DIV2 | OR_SCY_3_CLK)
448#define PUMA_CONF_READ_TIMING (OR_G5LA | OR_BI | OR_SCY_3_CLK)
449
450#define PUMA_CONF_BR_LOAD ((PUMA_CONF_BASE & BR_BA_MSK) | \
451 BR_PS_16 | BR_MS_UPMB | BR_V)
452#define PUMA_CONF_OR_LOAD (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
453
454#define PUMA_CONF_BR_READ ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
455#define PUMA_CONF_OR_READ (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
456
457#if PCU_E_WITH_SWAPPED_CS /* XXX */
458#define CFG_BR3_PRELIM PUMA_CONF_BR_READ
459#define CFG_OR3_PRELIM PUMA_CONF_OR_READ
460#else /* XXX */
461#define CFG_BR4_PRELIM PUMA_CONF_BR_READ
462#define CFG_OR4_PRELIM PUMA_CONF_OR_READ
463#endif /* XXX */
464
465/*
466 * BR5/OR5: PUMA: SMA Bus 8 Bit
467 * BR5: 0x10200401 OR5: 0xffe0010a
468 */
469#define PUMA_SMA8_BASE 0x10200000 /* PUMA SMA Bus 8 Bit */
470#define PUMA_SMA8_OR_AM 0xFFE00000 /* 2 MB */
471#define PUMA_SMA8_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
472
473#if PCU_E_WITH_SWAPPED_CS /* XXX */
474#define CFG_BR2_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
475#define CFG_OR2_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
476#else /* XXX */
477#define CFG_BR5_PRELIM ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
478#define CFG_OR5_PRELIM (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
479#endif /* XXX */
480
481/*
482 * BR6/OR6: PUMA: SMA Bus 16 Bit
483 * BR6: 0x10600801 OR6: 0xffe0010a
484 */
485#define PUMA_SMA16_BASE 0x10600000 /* PUMA SMA Bus 16 Bit */
486#define PUMA_SMA16_OR_AM 0xFFE00000 /* 2 MB */
487#define PUMA_SMA16_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
488
489#if PCU_E_WITH_SWAPPED_CS /* XXX */
490#define CFG_BR1_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
491#define CFG_OR1_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
492#else /* XXX */
493#define CFG_BR6_PRELIM ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
494#define CFG_OR6_PRELIM (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
495#endif /* XXX */
496
497/*
498 * BR7/OR7: PUMA: external Flash
499 * BR7: 0x10a00801 OR7: 0xfe00010a
500 */
501#define PUMA_FLASH_BASE 0x10A00000 /* PUMA external Flash */
502#define PUMA_FLASH_OR_AM 0xFE000000 /* 32 MB */
503#define PUMA_FLASH_TIMING (OR_BI | OR_SCY_0_CLK | OR_EHTR)
504
505#define CFG_BR7_PRELIM ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
506#define CFG_OR7_PRELIM (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
507
508/*
509 * Memory Periodic Timer Prescaler
510 */
511
512/* periodic timer for refresh */
513#define CFG_MPTPR 0x0200
514
515/*
516 * MAMR settings for SDRAM
517 * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
518 * MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
519 * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
520 */
521/* periodic timer for refresh */
522#define CFG_MAMR_PTA 0x30 /* = 48 */
523
524#define CFG_MAMR ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
wdenk2535d602003-07-17 23:16:40 +0000525 MAMR_AMA_TYPE_1 | \
526 MAMR_G0CLA_A10 | \
527 MAMR_RLFA_1X | \
528 MAMR_WLFA_1X | \
529 MAMR_TLFA_8X )
wdenk0f8c9762002-08-19 11:57:05 +0000530
531/*
532 * Internal Definitions
533 *
534 * Boot Flags
535 */
536#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
537#define BOOTFLAG_WARM 0x02 /* Software reboot */
538
539#endif /* __CONFIG_H */