blob: 32faa61607bca133eab2461ec01e52961414c461 [file] [log] [blame]
wdenk3bbc8992003-12-07 22:27:15 +00001/*
2 * (C) Copyright 2003
3 * MuLogic B.V.
4 *
5 * (C) Copyright 2002
6 * Simple Network Magic Corporation
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/* various debug settings */
38#undef CFG_DEVICE_NULLDEV /* null device */
39#undef CONFIG_SILENT_CONSOLE /* silent console */
40#undef CFG_CONSOLE_INFO_QUIET /* silent console ? */
41#undef DEBUG /* debug output code */
42#undef DEBUG_FLASH /* debug flash code */
43#undef FLASH_DEBUG /* debug fash code */
44#undef DEBUG_ENV /* debug environment code */
45
46#define CFG_DIRECT_FLASH_TFTP 1 /* allow direct tftp to flash */
47#define CONFIG_ENV_OVERWRITE 1 /* allow overwrite MAC address */
48
49
wdenk3bbc8992003-12-07 22:27:15 +000050/*
51 * High Level Configuration Options
52 * (easy to change)
53 */
54
55#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
56#define CONFIG_QS860T 1 /* ...on a QS860T module */
57
58#define CONFIG_FEC_ENET 1 /* FEC 10/100BaseT ethernet */
Marian Balakowicz63ff0042005-10-28 22:30:33 +020059#define CONFIG_MII
wdenk3bbc8992003-12-07 22:27:15 +000060#define FEC_INTERRUPT SIU_LEVEL1
61#undef CONFIG_SCC1_ENET /* SCC1 10BaseT ethernet */
62#define CFG_DISCOVER_PHY
63
64#undef CONFIG_8xx_CONS_SMC1
65#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC */
66#undef CONFIG_8xx_CONS_NONE
67
68#define CONFIG_BAUDRATE 38400 /* console baudrate = 38.4kbps */
69
70#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
71
72/* Pass clocks to Linux 2.4.18 in Hz */
73#undef CONFIG_CLOCKS_IN_MHZ /* clocks passsed to Linux in MHz */
74
75#define CONFIG_PREBOOT "echo;" \
76 "echo 'Type \"run flash_nfs\" to mount root filesystem over NFS';" \
77 "echo"
78
79#undef CONFIG_BOOTARGS
80/* TODO compare against CADM860 */
81#define CONFIG_BOOTCOMMAND "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010082 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
83 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk3bbc8992003-12-07 22:27:15 +000084 "bootm"
85
86#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
87#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
88
89#undef CONFIG_WATCHDOG /* watchdog disabled */
90
91#undef CONFIG_STATUS_LED /* Status LED disabled */
92
93#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
94
95#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
96
97#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
100#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
101
102#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
103 CFG_CMD_REGINFO | \
104 CFG_CMD_IMMAP | \
105 CFG_CMD_ASKENV | \
106 CFG_CMD_NET | \
107 CFG_CMD_DHCP | \
108 CFG_CMD_DATE )
109
110/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
111#include <cmd_confdefs.h>
112
113
114/* TODO */
115#if 0
116/* Look at these */
117CONFIG_IPADDR
118CONFIG_SERVERIP
119CONFIG_I2C
120CONFIG_SPI
121#endif
122
123/*
124 * Environment variable storage is in NVRAM
125 */
126#define CFG_ENV_IS_IN_NVRAM 1
127#define CFG_ENV_SIZE 0x00001000 /* We use only the last 4K for PPCBoot */
128#define CFG_ENV_ADDR 0xD100E000
129
130/*
131 * Miscellaneous configurable options
132 */
133#define CFG_LONGHELP /* undef to save memory */
134#define CFG_PROMPT "=> " /* Monitor Command Prompt */
135
136#define CFG_HUSH_PARSER 1 /* use "hush" command parser */
137#define CFG_PROMPT_HUSH_PS2 "> "
138
139#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
140#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
141#else
142#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
143#endif
144#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
145#define CFG_MAXARGS 16 /* max number of command args */
146#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
147
148/* TODO - size? */
149#define CFG_MEMTEST_START 0x0400000 /* memtest works */
150#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
151
152#define CFG_LOAD_ADDR 0x100000 /* default load address */
153
154#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
155
156#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
157
158/*-----------------------------------------------------------------------
159 * Low Level Configuration Settings
160 * (address mappings, register initial values, etc.)
161 * You should know what you are doing if you make changes here.
162 */
163/*-----------------------------------------------------------------------
164 * Internal Memory Mapped Register
165 */
166#define CFG_IMMR 0xF0000000
167
168/*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area (in DPRAM)
170 */
171#define CFG_INIT_RAM_ADDR CFG_IMMR
172#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
173#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
174#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
175#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
176
177/*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration
179 * (Set up by the startup code)
180 * Please note that CFG_SDRAM_BASE _must_ start at 0
181 */
182#define CFG_SDRAM_BASE 0x00000000
183#define CFG_FLASH_BASE 0xFFF00000
184
185#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
186#define CFG_MONITOR_BASE CFG_FLASH_BASE
187#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
188
189/*
190 * For booting Linux, the board info and command line data
191 * have to be in the first 8 MB of memory, since this is
192 * the maximum mapped by the Linux kernel during initialization.
193 */
194#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
195
196/* TODO flash parameters */
197/*-----------------------------------------------------------------------
198 * FLASH organization for Intel Strataflash
199 */
200#define CFG_FLASH_16BIT 1 /* 16-bit wide flash memory */
201#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
202#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
203
204#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
205#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
206
207#undef CFG_ENV_IS_IN_FLASH
208
209/*-----------------------------------------------------------------------
210 * Cache Configuration
211 */
212#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
213#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
214#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
215#endif
216
217/*-----------------------------------------------------------------------
218 * SYPCR - System Protection Control 11-9
219 * SYPCR can only be written once after reset!
220 *-----------------------------------------------------------------------
221 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
222 */
223#if defined(CONFIG_WATCHDOG)
224#define CFG_SYPCR (0xFFFFFF88 | SYPCR_SWE | SYPCR_SWRI)
225#else
226#define CFG_SYPCR 0xFFFFFF88
227#endif
228
229/*-----------------------------------------------------------------------
230 * SIUMCR - SIU Module Configuration 11-6
231 *-----------------------------------------------------------------------
232 */
233#define CFG_SIUMCR 0x00620000
234
235/*-----------------------------------------------------------------------
236 * TBSCR - Time Base Status and Control 11-26
237 *-----------------------------------------------------------------------
238 */
239#define CFG_TBSCR 0x00C3
240
241/*-----------------------------------------------------------------------
242 * RTCSC - Real-Time Clock Status and Control Register 11-27
243 *-----------------------------------------------------------------------
244 */
245#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
246
247/*-----------------------------------------------------------------------
248 * PISCR - Periodic Interrupt Status and Control 11-31
249 *-----------------------------------------------------------------------
250 */
251#define CFG_PISCR 0x0082
252
253/*-----------------------------------------------------------------------
254 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
255 *-----------------------------------------------------------------------
256 */
257#define CFG_PLPRCR 0x0090D000
258
259/*-----------------------------------------------------------------------
260 * SCCR - System Clock and reset Control Register 15-27
261 *-----------------------------------------------------------------------
262 */
263#define SCCR_MASK SCCR_EBDF11
264#define CFG_SCCR 0x02000000
265
266
267/*-----------------------------------------------------------------------
268 * Debug Enable Register
269 * 0x73E67C0F - All interrupts handled by BDM
270 * 0x00824001 - Only interrupts needed by MWDebug.exe handled by BDM
271 *-----------------------------------------------------------------------
272#define CFG_DER 0x73E67C0F
273*/
274#define CFG_DER 0x0082400F
275
276
277/*-----------------------------------------------------------------------
278 * Memory Controller Initialization Constants
279 *-----------------------------------------------------------------------
280 */
281
282/*
283 * BR0 and OR0 (AMD 512K Socketed FLASH)
284 * Base address = 0xFFF0_0000 - 0xFFF7_FFFF (After relocation)
285 */
286#define CFG_PRELIM_OR_AM
287#define CFG_OR_TIMING_FLASH
288
289#define FLASH_BASE0_PRELIM 0xFFF00001
290#define CFG_OR0_PRELIM 0xFFF80D42
291#define CFG_BR0_PRELIM 0xFFF00401
292
293
294/*
295 * BR1 and OR1 (Intel 8M StrataFLASH)
296 * Base address = 0xD000_0000 - 0xD07F_FFFF
297 */
298
299#define FLASH_BASE1_PRELIM 0xD0000000
300#define CFG_OR1_PRELIM 0xFF800D42
301#define CFG_BR1_PRELIM 0xD0000801
302/* #define CFG_OR1 0xFF800D42 */
303/* #define CFG_BR1 0xD0000801 */
304
305
306/*
307 * BR2 and OR2 (SDRAM)
308 * Base Address = 0x00000000 - 0x00FF_FFFF (16M After relocation)
309 * Base Address = 0x00000000 - 0x03FF_FFFF (64M After relocation)
310 * Base Address = 0x00000000 - 0x07FF_FFFF (128M After relocation)
311 *
312 */
313#define SDRAM_BASE 0x00000000 /* SDRAM bank */
314#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
315
316/* SDRAM timing */
317#define SDRAM_TIMING 0x00000A00
318
319/* For boards with 16M of SDRAM */
320#define SDRAM_16M_MAX_SIZE 0x01000000 /* max 16MB SDRAM */
321#define CFG_16M_MBMR 0x18802114 /* Mem Periodic Timer Prescaler */
322
323/* For boards with 64M of SDRAM */
324#define SDRAM_64M_MAX_SIZE 0x04000000 /* max 64MB SDRAM */
325/* TODO - determine real value */
326#define CFG_64M_MBMR 0x18802114 /* Mem Period Timer Prescaler */
327
328#define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING)
329#define CFG_BR2 (SDRAM_BASE | 0x000000C1)
330
331
332/*
333 * BR3 and OR3 (NVRAM, Sipex, NAND Flash)
334 * Base address = 0xD100_0000 - 0xD100_FFFF (64K NVRAM)
335 * Base address = 0xD108_0000 - 0xD108_0000 (Sipex chip ctl register)
336 * Base address = 0xD110_0000 - 0xD110_0000 (NAND ctl register)
337 * Base address = 0xD138_0000 - 0xD138_0000 (LED ctl register)
338 *
339 */
340
341#define CFG_OR3_PRELIM 0xFFC00DF6
342#define CFG_BR3_PRELIM 0xD1000401
343/* #define CFG_OR3 0xFFC00DF6 */
344/* #define CFG_BR3 0xD1000401 */
345
346
347/*
348 * BR4 and OR4 (Unused)
349 * Base address = 0xE000_0000 - 0xE3FF_FFFF
350 *
351 */
352
353#define CFG_OR4_PRELIM 0xFF000000
354#define CFG_BR4_PRELIM 0xE0000000
355/* #define CFG_OR4 0xFF000000 */
356/* #define CFG_BR4 0xE0000000 */
357
358
359/*
360 * BR5 and OR5 (Expansion bus)
361 * Base address = 0xE400_0000 - 0xE7FF_FFFF
362 *
363 */
364
365#define CFG_OR5_PRELIM 0xFF000000
366#define CFG_BR5_PRELIM 0xE4000000
367/* #define CFG_OR5 0xFF000000 */
368/* #define CFG_BR5 0xE4000000 */
369
370
wdenk3bbc8992003-12-07 22:27:15 +0000371/*
372 * BR6 and OR6 (Expansion bus)
373 * Base address = 0xE800_0000 - 0xEBFF_FFFF
374 *
375 */
376
377#define CFG_OR6_PRELIM 0xFF000000
378#define CFG_BR6_PRELIM 0xE8000000
379/* #define CFG_OR6 0xFF000000 */
380/* #define CFG_BR6 0xE8000000 */
381
382
wdenk3bbc8992003-12-07 22:27:15 +0000383/*
384 * BR7 and OR7 (Expansion bus)
385 * Base address = 0xEC00_0000 - 0xEFFF_FFFF
386 *
387 */
388
389#define CFG_OR7_PRELIM 0xFF000000
390#define CFG_BR7_PRELIM 0xE8000000
391/* #define CFG_OR7 0xFF000000 */
392/* #define CFG_BR7 0xE8000000 */
393
394
wdenk3bbc8992003-12-07 22:27:15 +0000395/*
396 * Internal Definitions
397 *
398 * Boot Flags
399 */
400#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
401#define BOOTFLAG_WARM 0x02 /* Software reboot */
402
403/*
404 * Sanity checks
405 */
406#if defined(CONFIG_SCC1_ENET) && defined(CONFIG_FEC_ENET)
407#error Both CONFIG_SCC1_ENET and CONFIG_FEC_ENET configured
408#endif
409
410#endif /* __CONFIG_H */