Simon Glass | afb6134 | 2013-12-03 16:43:25 -0700 | [diff] [blame] | 1 | SPI (Serial Peripheral Interface) busses |
| 2 | |
| 3 | SPI busses can be described with a node for the SPI master device |
| 4 | and a set of child nodes for each SPI slave on the bus. For this |
| 5 | discussion, it is assumed that the system's SPI controller is in |
| 6 | SPI master mode. This binding does not describe SPI controllers |
| 7 | in slave mode. |
| 8 | |
| 9 | The SPI master node requires the following properties: |
| 10 | - #address-cells - number of cells required to define a chip select |
| 11 | address on the SPI bus. |
| 12 | - #size-cells - should be zero. |
| 13 | - compatible - name of SPI bus controller following generic names |
| 14 | recommended practice. |
| 15 | - cs-gpios - (optional) gpios chip select. |
| 16 | No other properties are required in the SPI bus node. It is assumed |
| 17 | that a driver for an SPI bus device will understand that it is an SPI bus. |
| 18 | However, the binding does not attempt to define the specific method for |
| 19 | assigning chip select numbers. Since SPI chip select configuration is |
| 20 | flexible and non-standardized, it is left out of this binding with the |
| 21 | assumption that board specific platform code will be used to manage |
| 22 | chip selects. Individual drivers can define additional properties to |
| 23 | support describing the chip select layout. |
| 24 | |
| 25 | Optional property: |
| 26 | - num-cs : total number of chipselects |
| 27 | |
| 28 | If cs-gpios is used the number of chip select will automatically increased |
| 29 | with max(cs-gpios > hw cs) |
| 30 | |
| 31 | So if for example the controller has 2 CS lines, and the cs-gpios |
| 32 | property looks like this: |
| 33 | |
| 34 | cs-gpios = <&gpio1 0 0> <0> <&gpio1 1 0> <&gpio1 2 0>; |
| 35 | |
| 36 | Then it should be configured so that num_chipselect = 4 with the |
| 37 | following mapping: |
| 38 | |
| 39 | cs0 : &gpio1 0 0 |
| 40 | cs1 : native |
| 41 | cs2 : &gpio1 1 0 |
| 42 | cs3 : &gpio1 2 0 |
| 43 | |
| 44 | SPI slave nodes must be children of the SPI master node and can |
| 45 | contain the following properties. |
| 46 | - reg - (required) chip select address of device. |
| 47 | - compatible - (required) name of SPI device following generic names |
| 48 | recommended practice |
| 49 | - spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz |
| 50 | - spi-cpol - (optional) Empty property indicating device requires |
| 51 | inverse clock polarity (CPOL) mode |
| 52 | - spi-cpha - (optional) Empty property indicating device requires |
| 53 | shifted clock phase (CPHA) mode |
| 54 | - spi-cs-high - (optional) Empty property indicating device requires |
| 55 | chip select active high |
| 56 | - spi-3wire - (optional) Empty property indicating device requires |
| 57 | 3-wire mode. |
| 58 | - spi-tx-bus-width - (optional) The bus width(number of data wires) that |
| 59 | used for MOSI. Defaults to 1 if not present. |
| 60 | - spi-rx-bus-width - (optional) The bus width(number of data wires) that |
| 61 | used for MISO. Defaults to 1 if not present. |
Simon Glass | 22052c6 | 2014-07-07 10:16:39 -0600 | [diff] [blame] | 62 | - spi-half-duplex - (optional) Indicates that the SPI bus should wait for |
| 63 | a header byte before reading data from the slave. |
Simon Glass | afb6134 | 2013-12-03 16:43:25 -0700 | [diff] [blame] | 64 | |
| 65 | Some SPI controllers and devices support Dual and Quad SPI transfer mode. |
| 66 | It allows data in SPI system transfered in 2 wires(DUAL) or 4 wires(QUAD). |
| 67 | Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is |
| 68 | only 1(SINGLE), 2(DUAL) and 4(QUAD). |
| 69 | Dual/Quad mode is not allowed when 3-wire mode is used. |
| 70 | |
| 71 | If a gpio chipselect is used for the SPI slave the gpio number will be passed |
| 72 | via the cs_gpio |
| 73 | |
| 74 | SPI example for an MPC5200 SPI bus: |
| 75 | spi@f00 { |
| 76 | #address-cells = <1>; |
| 77 | #size-cells = <0>; |
| 78 | compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi"; |
| 79 | reg = <0xf00 0x20>; |
| 80 | interrupts = <2 13 0 2 14 0>; |
| 81 | interrupt-parent = <&mpc5200_pic>; |
| 82 | |
| 83 | ethernet-switch@0 { |
| 84 | compatible = "micrel,ks8995m"; |
| 85 | spi-max-frequency = <1000000>; |
| 86 | reg = <0>; |
| 87 | }; |
| 88 | |
| 89 | codec@1 { |
| 90 | compatible = "ti,tlv320aic26"; |
| 91 | spi-max-frequency = <100000>; |
| 92 | reg = <1>; |
| 93 | }; |
| 94 | }; |