blob: ff278ae9f1095d3147194142c6c00d80d64f78d0 [file] [log] [blame]
Xie Xiaobo49f5bef2013-06-24 15:01:30 +08001/*
2 * Copyright 2013 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
10#include <asm/mmu.h>
11#include <asm/immap_85xx.h>
12#include <asm/processor.h>
13#include <asm/fsl_ddr_sdram.h>
14#include <asm/fsl_ddr_dimm_params.h>
15#include <asm/io.h>
16#include <asm/fsl_law.h>
17
18/* Fixed sdram init -- doesn't use serial presence detect. */
19phys_size_t fixed_sdram(void)
20{
21 sys_info_t sysinfo;
22 char buf[32];
23 size_t ddr_size;
24 fsl_ddr_cfg_regs_t ddr_cfg_regs = {
25 .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
26 .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
27 .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
28#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
29 .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
30 .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
31 .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
32#endif
33 .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
34 .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
35 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
36 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
37 .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
38 .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
39 .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
40 .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
41 .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
42 .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
43 .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
44 .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
45 .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
46 .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
47 .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
48 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
49 .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
50 .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
51 .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
52 .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
53 .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
54 };
55
56 get_sys_info(&sysinfo);
57 printf("Configuring DDR for %s MT/s data rate\n",
58 strmhz(buf, sysinfo.freqDDRBus));
59
60 ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
61
62 fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
63
64 if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
65 ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
66 printf("ERROR setting Local Access Windows for DDR\n");
67 return 0;
68 };
69
70 return ddr_size;
71}