blob: edc565ef723c11f390b2092f82fadf0678846401 [file] [log] [blame]
Chander Kashyap0aee53b2012-02-05 23:01:47 +00001/*
2 * Lowlevel setup for SMDK5250 board based on S5PC520
3 *
4 * Copyright (C) 2012 Samsung Electronics
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <config.h>
26#include <version.h>
27#include <asm/arch/cpu.h>
28
29_TEXT_BASE:
30 .word CONFIG_SYS_TEXT_BASE
31
32 .globl lowlevel_init
33lowlevel_init:
34
35 /* use iRAM stack in bl2 */
36 ldr sp, =CONFIG_IRAM_STACK
37 stmdb r13!, {ip,lr}
38
39 /* check reset status */
40 ldr r0, =(EXYNOS5_POWER_BASE + INFORM1_OFFSET)
41 ldr r1, [r0]
42
43 /* AFTR wakeup reset */
44 ldr r2, =S5P_CHECK_DIDLE
45 cmp r1, r2
46 beq exit_wakeup
47
48 /* LPA wakeup reset */
49 ldr r2, =S5P_CHECK_LPA
50 cmp r1, r2
51 beq exit_wakeup
52
53 /* Sleep wakeup reset */
54 ldr r2, =S5P_CHECK_SLEEP
55 cmp r1, r2
56 beq wakeup_reset
57
58 /*
59 * If U-boot is already running in RAM, no need to relocate U-Boot.
60 * Memory controller must be configured before relocating U-Boot
61 * in ram.
62 */
63 ldr r0, =0x0ffffff /* r0 <- Mask Bits*/
64 bic r1, pc, r0 /* pc <- current addr of code */
65 /* r1 <- unmasked bits of pc */
66 ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
67 bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
68 cmp r1, r2 /* compare r1, r2 */
69 beq 1f /* r0 == r1 then skip sdram init */
70
71 /* init system clock */
72 bl system_clock_init
73
74 /* Memory initialize */
75 bl mem_ctrl_init
76
771:
Inderpal Singhb5f97562013-04-04 23:09:20 +000078 bl arch_cpu_init
Chander Kashyap0aee53b2012-02-05 23:01:47 +000079 bl tzpc_init
80 ldmia r13!, {ip,pc}
81
82wakeup_reset:
83 bl system_clock_init
84 bl mem_ctrl_init
Inderpal Singhb5f97562013-04-04 23:09:20 +000085 bl arch_cpu_init
Chander Kashyap0aee53b2012-02-05 23:01:47 +000086 bl tzpc_init
87
88exit_wakeup:
89 /* Load return address and jump to kernel */
90 ldr r0, =(EXYNOS5_POWER_BASE + INFORM0_OFFSET)
91
92 /* r1 = physical address of exynos5_cpu_resume function*/
93 ldr r1, [r0]
94
95 /* Jump to kernel */
96 mov pc, r1
97 nop
98 nop