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Cliff Cai716ebf42008-11-29 18:22:38 -05001/*
2 * Driver for Blackfin on-chip SDH controller
3 *
Cliff Caie54c8202009-11-20 08:24:43 +00004 * Copyright (c) 2008-2009 Analog Devices Inc.
Cliff Cai716ebf42008-11-29 18:22:38 -05005 *
6 * Licensed under the GPL-2 or later.
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include <part.h>
12#include <mmc.h>
13
14#include <asm/io.h>
15#include <asm/errno.h>
16#include <asm/byteorder.h>
17#include <asm/blackfin.h>
Tom Rini130fbeb2014-02-20 10:14:10 -050018#include <asm/clock.h>
Mike Frysingera87589f2010-06-02 05:59:50 -040019#include <asm/portmux.h>
Cliff Cai716ebf42008-11-29 18:22:38 -050020#include <asm/mach-common/bits/sdh.h>
21#include <asm/mach-common/bits/dma.h>
22
Sonic Zhang187f32f2012-08-16 11:26:00 +080023#if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__)
Cliff Cai716ebf42008-11-29 18:22:38 -050024# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
25# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
26# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
27# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
28# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
29# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
30# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
31# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
32# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
33# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
34# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
35# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
36# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
37# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
38# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
39# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
Sonic Zhang187f32f2012-08-16 11:26:00 +080040# if defined(__ADSPBF60x__)
41# define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ
42# define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ
43# define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR
44# define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT
45# define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY
46# define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG
47# else
48# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
49# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
Cliff Cai716ebf42008-11-29 18:22:38 -050050# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
51# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
52# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
53# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
Sonic Zhang187f32f2012-08-16 11:26:00 +080054# endif
Mike Frysingera87589f2010-06-02 05:59:50 -040055# define PORTMUX_PINS \
56 { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 }
Cliff Cai716ebf42008-11-29 18:22:38 -050057#elif defined(__ADSPBF54x__)
58# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
59# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
60# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
61# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
Mike Frysingera87589f2010-06-02 05:59:50 -040062# define PORTMUX_PINS \
63 { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 }
Cliff Cai716ebf42008-11-29 18:22:38 -050064#else
65# error no support for this proc yet
66#endif
67
Cliff Cai716ebf42008-11-29 18:22:38 -050068static int
Cliff Caie54c8202009-11-20 08:24:43 +000069sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
Cliff Cai716ebf42008-11-29 18:22:38 -050070{
Mike Frysinger6815f542010-06-21 20:56:54 +000071 unsigned int status, timeout;
Cliff Caie54c8202009-11-20 08:24:43 +000072 int cmd = mmc_cmd->cmdidx;
73 int flags = mmc_cmd->resp_type;
74 int arg = mmc_cmd->cmdarg;
Mike Frysinger6815f542010-06-21 20:56:54 +000075 int ret;
76 u16 sdh_cmd;
Cliff Caie54c8202009-11-20 08:24:43 +000077
Mike Frysinger6815f542010-06-21 20:56:54 +000078 sdh_cmd = cmd | CMD_E;
Cliff Cai716ebf42008-11-29 18:22:38 -050079 if (flags & MMC_RSP_PRESENT)
80 sdh_cmd |= CMD_RSP;
Cliff Cai716ebf42008-11-29 18:22:38 -050081 if (flags & MMC_RSP_136)
82 sdh_cmd |= CMD_L_RSP;
Sonic Zhang187f32f2012-08-16 11:26:00 +080083#ifdef RSI_BLKSZ
84 sdh_cmd |= CMD_DATA0_BUSY;
85#endif
Cliff Cai716ebf42008-11-29 18:22:38 -050086
87 bfin_write_SDH_ARGUMENT(arg);
Mike Frysinger6815f542010-06-21 20:56:54 +000088 bfin_write_SDH_COMMAND(sdh_cmd);
Cliff Cai716ebf42008-11-29 18:22:38 -050089
90 /* wait for a while */
Mike Frysinger6815f542010-06-21 20:56:54 +000091 timeout = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -050092 do {
Mike Frysinger6815f542010-06-21 20:56:54 +000093 if (++timeout > 1000000) {
94 status = CMD_TIME_OUT;
95 break;
96 }
Cliff Cai716ebf42008-11-29 18:22:38 -050097 udelay(1);
98 status = bfin_read_SDH_STATUS();
99 } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
100 CMD_CRC_FAIL)));
101
102 if (flags & MMC_RSP_PRESENT) {
Cliff Caie54c8202009-11-20 08:24:43 +0000103 mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0();
Cliff Cai716ebf42008-11-29 18:22:38 -0500104 if (flags & MMC_RSP_136) {
Cliff Caie54c8202009-11-20 08:24:43 +0000105 mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1();
106 mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2();
107 mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3();
Cliff Cai716ebf42008-11-29 18:22:38 -0500108 }
109 }
110
Cliff Caie54c8202009-11-20 08:24:43 +0000111 if (status & CMD_TIME_OUT)
Mike Frysinger6815f542010-06-21 20:56:54 +0000112 ret = TIMEOUT;
Cliff Caie54c8202009-11-20 08:24:43 +0000113 else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC)
Mike Frysinger6815f542010-06-21 20:56:54 +0000114 ret = COMM_ERR;
115 else
116 ret = 0;
Cliff Caie54c8202009-11-20 08:24:43 +0000117
Cliff Cai716ebf42008-11-29 18:22:38 -0500118 bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
119 CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
Sonic Zhang187f32f2012-08-16 11:26:00 +0800120#ifdef RSI_BLKSZ
121 /* wait till card ready */
122 while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY))
123 continue;
124 bfin_write_RSI_ESTAT(SD_CARD_READY);
125#endif
Mike Frysinger6815f542010-06-21 20:56:54 +0000126
Cliff Cai716ebf42008-11-29 18:22:38 -0500127 return ret;
128}
129
Cliff Caie54c8202009-11-20 08:24:43 +0000130/* set data for single block transfer */
131static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data)
Cliff Cai716ebf42008-11-29 18:22:38 -0500132{
Cliff Caie54c8202009-11-20 08:24:43 +0000133 u16 data_ctl = 0;
134 u16 dma_cfg = 0;
Sonic Zhang21a50372010-12-30 08:38:00 +0000135 unsigned long data_size = data->blocksize * data->blocks;
Cliff Cai716ebf42008-11-29 18:22:38 -0500136
Cliff Caie54c8202009-11-20 08:24:43 +0000137 /* Don't support write yet. */
138 if (data->flags & MMC_DATA_WRITE)
139 return UNUSABLE_ERR;
Sonic Zhang187f32f2012-08-16 11:26:00 +0800140#ifndef RSI_BLKSZ
Sonic Zhang282a82e2014-08-06 18:14:35 +0800141 data_ctl |= ((ffs(data->blocksize) - 1) << 4);
Sonic Zhang187f32f2012-08-16 11:26:00 +0800142#else
Sonic Zhang282a82e2014-08-06 18:14:35 +0800143 bfin_write_SDH_BLK_SIZE(data->blocksize);
Sonic Zhang187f32f2012-08-16 11:26:00 +0800144#endif
Cliff Caie54c8202009-11-20 08:24:43 +0000145 data_ctl |= DTX_DIR;
146 bfin_write_SDH_DATA_CTL(data_ctl);
Sonic Zhang187f32f2012-08-16 11:26:00 +0800147 dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN;
Cliff Cai716ebf42008-11-29 18:22:38 -0500148
Cliff Cai1fd2d792009-12-07 06:12:11 +0000149 bfin_write_SDH_DATA_TIMER(-1);
Cliff Caie54c8202009-11-20 08:24:43 +0000150
151 blackfin_dcache_flush_invalidate_range(data->dest,
Sonic Zhang21a50372010-12-30 08:38:00 +0000152 data->dest + data_size);
Cliff Caie54c8202009-11-20 08:24:43 +0000153 /* configure DMA */
154 bfin_write_DMA_START_ADDR(data->dest);
Sonic Zhang21a50372010-12-30 08:38:00 +0000155 bfin_write_DMA_X_COUNT(data_size / 4);
Cliff Caie54c8202009-11-20 08:24:43 +0000156 bfin_write_DMA_X_MODIFY(4);
157 bfin_write_DMA_CONFIG(dma_cfg);
Sonic Zhang21a50372010-12-30 08:38:00 +0000158 bfin_write_SDH_DATA_LGTH(data_size);
Cliff Caie54c8202009-11-20 08:24:43 +0000159 /* kick off transfer */
160 bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
161
Sonic Zhang187f32f2012-08-16 11:26:00 +0800162 return 0;
Cliff Cai716ebf42008-11-29 18:22:38 -0500163}
164
Cliff Caie54c8202009-11-20 08:24:43 +0000165
166static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd,
167 struct mmc_data *data)
Cliff Cai716ebf42008-11-29 18:22:38 -0500168{
Cliff Caie54c8202009-11-20 08:24:43 +0000169 u32 status;
170 int ret = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -0500171
Sonic Zhang187f32f2012-08-16 11:26:00 +0800172 if (data) {
173 ret = sdh_setup_data(mmc, data);
174 if (ret)
175 return ret;
176 }
177
Cliff Caie54c8202009-11-20 08:24:43 +0000178 ret = sdh_send_cmd(mmc, cmd);
179 if (ret) {
Sonic Zhang187f32f2012-08-16 11:26:00 +0800180 bfin_write_SDH_COMMAND(0);
181 bfin_write_DMA_CONFIG(0);
182 bfin_write_SDH_DATA_CTL(0);
183 SSYNC();
Cliff Caie54c8202009-11-20 08:24:43 +0000184 printf("sending CMD%d failed\n", cmd->cmdidx);
185 return ret;
186 }
Sonic Zhang187f32f2012-08-16 11:26:00 +0800187
Cliff Caie54c8202009-11-20 08:24:43 +0000188 if (data) {
Cliff Cai716ebf42008-11-29 18:22:38 -0500189 do {
190 udelay(1);
191 status = bfin_read_SDH_STATUS();
Sonic Zhang282a82e2014-08-06 18:14:35 +0800192 } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL |
193 RX_OVERRUN)));
Cliff Cai716ebf42008-11-29 18:22:38 -0500194
Cliff Caie54c8202009-11-20 08:24:43 +0000195 if (status & DAT_TIME_OUT) {
196 bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT);
197 ret |= TIMEOUT;
198 } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) {
199 bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
200 ret |= COMM_ERR;
201 } else
Cliff Cai716ebf42008-11-29 18:22:38 -0500202 bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
Cliff Caie54c8202009-11-20 08:24:43 +0000203
204 if (ret) {
205 printf("tranfering data failed\n");
206 return ret;
Cliff Cai716ebf42008-11-29 18:22:38 -0500207 }
208 }
Cliff Cai716ebf42008-11-29 18:22:38 -0500209 return 0;
210}
211
Cliff Caie54c8202009-11-20 08:24:43 +0000212static void sdh_set_clk(unsigned long clk)
Cliff Cai716ebf42008-11-29 18:22:38 -0500213{
Cliff Caie54c8202009-11-20 08:24:43 +0000214 unsigned long sys_clk;
215 unsigned long clk_div;
216 u16 clk_ctl = 0;
Cliff Cai716ebf42008-11-29 18:22:38 -0500217
Cliff Caie54c8202009-11-20 08:24:43 +0000218 clk_ctl = bfin_read_SDH_CLK_CTL();
219 if (clk) {
220 /* setting SD_CLK */
221 sys_clk = get_sclk();
222 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
223 if (sys_clk % (2 * clk) == 0)
224 clk_div = sys_clk / (2 * clk) - 1;
225 else
226 clk_div = sys_clk / (2 * clk);
Cliff Cai716ebf42008-11-29 18:22:38 -0500227
Cliff Caie54c8202009-11-20 08:24:43 +0000228 if (clk_div > 0xff)
229 clk_div = 0xff;
230 clk_ctl |= (clk_div & 0xff);
231 clk_ctl |= CLK_E;
232 bfin_write_SDH_CLK_CTL(clk_ctl);
233 } else
234 bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E);
Cliff Cai716ebf42008-11-29 18:22:38 -0500235}
236
Cliff Caie54c8202009-11-20 08:24:43 +0000237static void bfin_sdh_set_ios(struct mmc *mmc)
Cliff Cai716ebf42008-11-29 18:22:38 -0500238{
Cliff Caie54c8202009-11-20 08:24:43 +0000239 u16 cfg = 0;
240 u16 clk_ctl = 0;
241
Tom Rini0b2da7e2014-03-28 16:55:29 -0400242 if (mmc->bus_width == 4) {
Cliff Caie54c8202009-11-20 08:24:43 +0000243 cfg = bfin_read_SDH_CFG();
Sonic Zhang187f32f2012-08-16 11:26:00 +0800244#ifndef RSI_BLKSZ
245 cfg &= ~PD_SDDAT3;
246#endif
247 cfg |= PUP_SDDAT3;
Cliff Caie54c8202009-11-20 08:24:43 +0000248 bfin_write_SDH_CFG(cfg);
Sonic Zhang187f32f2012-08-16 11:26:00 +0800249 clk_ctl |= WIDE_BUS_4;
Cliff Caie54c8202009-11-20 08:24:43 +0000250 }
251 bfin_write_SDH_CLK_CTL(clk_ctl);
252 sdh_set_clk(mmc->clock);
253}
254
255static int bfin_sdh_init(struct mmc *mmc)
256{
Mike Frysingera87589f2010-06-02 05:59:50 -0400257 const unsigned short pins[] = PORTMUX_PINS;
Sonic Zhang187f32f2012-08-16 11:26:00 +0800258 int ret;
Mike Frysingera87589f2010-06-02 05:59:50 -0400259
260 /* Initialize sdh controller */
Sonic Zhang187f32f2012-08-16 11:26:00 +0800261 ret = peripheral_request_list(pins, "bfin_sdh");
262 if (ret < 0)
263 return ret;
Cliff Cai716ebf42008-11-29 18:22:38 -0500264#if defined(__ADSPBF54x__)
265 bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
Cliff Cai716ebf42008-11-29 18:22:38 -0500266#endif
267 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
268 /* Disable card detect pin */
269 bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
Sonic Zhang187f32f2012-08-16 11:26:00 +0800270#ifndef RSI_BLKSZ
271 bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL);
272#else
273 bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON);
274#endif
Cliff Cai716ebf42008-11-29 18:22:38 -0500275 return 0;
276}
277
Pantelis Antoniouab769f22014-02-26 19:28:45 +0200278static const struct mmc_ops bfin_mmc_ops = {
279 .send_cmd = bfin_sdh_request,
280 .set_ios = bfin_sdh_set_ios,
281 .init = bfin_sdh_init,
282};
Cliff Caie54c8202009-11-20 08:24:43 +0000283
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200284static struct mmc_config bfin_mmc_cfg = {
285 .name = "Blackfin SDH",
286 .ops = &bfin_mmc_ops,
287 .host_caps = MMC_MODE_4BIT,
288 .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
289 .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
290};
291
Cliff Caie54c8202009-11-20 08:24:43 +0000292int bfin_mmc_init(bd_t *bis)
Cliff Cai716ebf42008-11-29 18:22:38 -0500293{
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200294 struct mmc *mmc;
Cliff Caie54c8202009-11-20 08:24:43 +0000295
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200296 bfin_mmc_cfg.f_max = get_sclk();
297 bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9;
Cliff Caie54c8202009-11-20 08:24:43 +0000298
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200299 mmc = mmc_create(&bfin_mmc_cfg, NULL);
300 if (mmc == NULL)
301 return -1;
Cliff Caie54c8202009-11-20 08:24:43 +0000302
Cliff Cai716ebf42008-11-29 18:22:38 -0500303 return 0;
304}