Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Blackfin on-chip SDH controller |
| 3 | * |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 4 | * Copyright (c) 2008-2009 Analog Devices Inc. |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 5 | * |
| 6 | * Licensed under the GPL-2 or later. |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <malloc.h> |
| 11 | #include <part.h> |
| 12 | #include <mmc.h> |
| 13 | |
| 14 | #include <asm/io.h> |
| 15 | #include <asm/errno.h> |
| 16 | #include <asm/byteorder.h> |
| 17 | #include <asm/blackfin.h> |
Tom Rini | 130fbeb | 2014-02-20 10:14:10 -0500 | [diff] [blame] | 18 | #include <asm/clock.h> |
Mike Frysinger | a87589f | 2010-06-02 05:59:50 -0400 | [diff] [blame] | 19 | #include <asm/portmux.h> |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 20 | #include <asm/mach-common/bits/sdh.h> |
| 21 | #include <asm/mach-common/bits/dma.h> |
| 22 | |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 23 | #if defined(__ADSPBF50x__) || defined(__ADSPBF51x__) || defined(__ADSPBF60x__) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 24 | # define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL |
| 25 | # define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL |
| 26 | # define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT |
| 27 | # define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND |
| 28 | # define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0 |
| 29 | # define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1 |
| 30 | # define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2 |
| 31 | # define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3 |
| 32 | # define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER |
| 33 | # define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH |
| 34 | # define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL |
| 35 | # define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL |
| 36 | # define bfin_read_SDH_STATUS bfin_read_RSI_STATUS |
| 37 | # define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL |
| 38 | # define bfin_read_SDH_CFG bfin_read_RSI_CONFIG |
| 39 | # define bfin_write_SDH_CFG bfin_write_RSI_CONFIG |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 40 | # if defined(__ADSPBF60x__) |
| 41 | # define bfin_read_SDH_BLK_SIZE bfin_read_RSI_BLKSZ |
| 42 | # define bfin_write_SDH_BLK_SIZE bfin_write_RSI_BLKSZ |
| 43 | # define bfin_write_DMA_START_ADDR bfin_write_DMA10_START_ADDR |
| 44 | # define bfin_write_DMA_X_COUNT bfin_write_DMA10_X_COUNT |
| 45 | # define bfin_write_DMA_X_MODIFY bfin_write_DMA10_X_MODIFY |
| 46 | # define bfin_write_DMA_CONFIG bfin_write_DMA10_CONFIG |
| 47 | # else |
| 48 | # define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL |
| 49 | # define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 50 | # define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR |
| 51 | # define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT |
| 52 | # define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY |
| 53 | # define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 54 | # endif |
Mike Frysinger | a87589f | 2010-06-02 05:59:50 -0400 | [diff] [blame] | 55 | # define PORTMUX_PINS \ |
| 56 | { P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3, P_RSI_CMD, P_RSI_CLK, 0 } |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 57 | #elif defined(__ADSPBF54x__) |
| 58 | # define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR |
| 59 | # define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT |
| 60 | # define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY |
| 61 | # define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG |
Mike Frysinger | a87589f | 2010-06-02 05:59:50 -0400 | [diff] [blame] | 62 | # define PORTMUX_PINS \ |
| 63 | { P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD, 0 } |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 64 | #else |
| 65 | # error no support for this proc yet |
| 66 | #endif |
| 67 | |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 68 | static int |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 69 | sdh_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 70 | { |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 71 | unsigned int status, timeout; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 72 | int cmd = mmc_cmd->cmdidx; |
| 73 | int flags = mmc_cmd->resp_type; |
| 74 | int arg = mmc_cmd->cmdarg; |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 75 | int ret; |
| 76 | u16 sdh_cmd; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 77 | |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 78 | sdh_cmd = cmd | CMD_E; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 79 | if (flags & MMC_RSP_PRESENT) |
| 80 | sdh_cmd |= CMD_RSP; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 81 | if (flags & MMC_RSP_136) |
| 82 | sdh_cmd |= CMD_L_RSP; |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 83 | #ifdef RSI_BLKSZ |
| 84 | sdh_cmd |= CMD_DATA0_BUSY; |
| 85 | #endif |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 86 | |
| 87 | bfin_write_SDH_ARGUMENT(arg); |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 88 | bfin_write_SDH_COMMAND(sdh_cmd); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 89 | |
| 90 | /* wait for a while */ |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 91 | timeout = 0; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 92 | do { |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 93 | if (++timeout > 1000000) { |
| 94 | status = CMD_TIME_OUT; |
| 95 | break; |
| 96 | } |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 97 | udelay(1); |
| 98 | status = bfin_read_SDH_STATUS(); |
| 99 | } while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT | |
| 100 | CMD_CRC_FAIL))); |
| 101 | |
| 102 | if (flags & MMC_RSP_PRESENT) { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 103 | mmc_cmd->response[0] = bfin_read_SDH_RESPONSE0(); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 104 | if (flags & MMC_RSP_136) { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 105 | mmc_cmd->response[1] = bfin_read_SDH_RESPONSE1(); |
| 106 | mmc_cmd->response[2] = bfin_read_SDH_RESPONSE2(); |
| 107 | mmc_cmd->response[3] = bfin_read_SDH_RESPONSE3(); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 108 | } |
| 109 | } |
| 110 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 111 | if (status & CMD_TIME_OUT) |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 112 | ret = TIMEOUT; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 113 | else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 114 | ret = COMM_ERR; |
| 115 | else |
| 116 | ret = 0; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 117 | |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 118 | bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT | |
| 119 | CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 120 | #ifdef RSI_BLKSZ |
| 121 | /* wait till card ready */ |
| 122 | while (!(bfin_read_RSI_ESTAT() & SD_CARD_READY)) |
| 123 | continue; |
| 124 | bfin_write_RSI_ESTAT(SD_CARD_READY); |
| 125 | #endif |
Mike Frysinger | 6815f54 | 2010-06-21 20:56:54 +0000 | [diff] [blame] | 126 | |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 127 | return ret; |
| 128 | } |
| 129 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 130 | /* set data for single block transfer */ |
| 131 | static int sdh_setup_data(struct mmc *mmc, struct mmc_data *data) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 132 | { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 133 | u16 data_ctl = 0; |
| 134 | u16 dma_cfg = 0; |
Sonic Zhang | 21a5037 | 2010-12-30 08:38:00 +0000 | [diff] [blame] | 135 | unsigned long data_size = data->blocksize * data->blocks; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 136 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 137 | /* Don't support write yet. */ |
| 138 | if (data->flags & MMC_DATA_WRITE) |
| 139 | return UNUSABLE_ERR; |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 140 | #ifndef RSI_BLKSZ |
Sonic Zhang | 282a82e | 2014-08-06 18:14:35 +0800 | [diff] [blame] | 141 | data_ctl |= ((ffs(data->blocksize) - 1) << 4); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 142 | #else |
Sonic Zhang | 282a82e | 2014-08-06 18:14:35 +0800 | [diff] [blame] | 143 | bfin_write_SDH_BLK_SIZE(data->blocksize); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 144 | #endif |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 145 | data_ctl |= DTX_DIR; |
| 146 | bfin_write_SDH_DATA_CTL(data_ctl); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 147 | dma_cfg = WDSIZE_32 | PSIZE_32 | RESTART | WNR | DMAEN; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 148 | |
Cliff Cai | 1fd2d79 | 2009-12-07 06:12:11 +0000 | [diff] [blame] | 149 | bfin_write_SDH_DATA_TIMER(-1); |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 150 | |
| 151 | blackfin_dcache_flush_invalidate_range(data->dest, |
Sonic Zhang | 21a5037 | 2010-12-30 08:38:00 +0000 | [diff] [blame] | 152 | data->dest + data_size); |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 153 | /* configure DMA */ |
| 154 | bfin_write_DMA_START_ADDR(data->dest); |
Sonic Zhang | 21a5037 | 2010-12-30 08:38:00 +0000 | [diff] [blame] | 155 | bfin_write_DMA_X_COUNT(data_size / 4); |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 156 | bfin_write_DMA_X_MODIFY(4); |
| 157 | bfin_write_DMA_CONFIG(dma_cfg); |
Sonic Zhang | 21a5037 | 2010-12-30 08:38:00 +0000 | [diff] [blame] | 158 | bfin_write_SDH_DATA_LGTH(data_size); |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 159 | /* kick off transfer */ |
| 160 | bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E); |
| 161 | |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 162 | return 0; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 163 | } |
| 164 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 165 | |
| 166 | static int bfin_sdh_request(struct mmc *mmc, struct mmc_cmd *cmd, |
| 167 | struct mmc_data *data) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 168 | { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 169 | u32 status; |
| 170 | int ret = 0; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 171 | |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 172 | if (data) { |
| 173 | ret = sdh_setup_data(mmc, data); |
| 174 | if (ret) |
| 175 | return ret; |
| 176 | } |
| 177 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 178 | ret = sdh_send_cmd(mmc, cmd); |
| 179 | if (ret) { |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 180 | bfin_write_SDH_COMMAND(0); |
| 181 | bfin_write_DMA_CONFIG(0); |
| 182 | bfin_write_SDH_DATA_CTL(0); |
| 183 | SSYNC(); |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 184 | printf("sending CMD%d failed\n", cmd->cmdidx); |
| 185 | return ret; |
| 186 | } |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 187 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 188 | if (data) { |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 189 | do { |
| 190 | udelay(1); |
| 191 | status = bfin_read_SDH_STATUS(); |
Sonic Zhang | 282a82e | 2014-08-06 18:14:35 +0800 | [diff] [blame] | 192 | } while (!(status & (DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | |
| 193 | RX_OVERRUN))); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 194 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 195 | if (status & DAT_TIME_OUT) { |
| 196 | bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT); |
| 197 | ret |= TIMEOUT; |
| 198 | } else if (status & (DAT_CRC_FAIL | RX_OVERRUN)) { |
| 199 | bfin_write_SDH_STATUS_CLR(DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT); |
| 200 | ret |= COMM_ERR; |
| 201 | } else |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 202 | bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT); |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 203 | |
| 204 | if (ret) { |
| 205 | printf("tranfering data failed\n"); |
| 206 | return ret; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 207 | } |
| 208 | } |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 209 | return 0; |
| 210 | } |
| 211 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 212 | static void sdh_set_clk(unsigned long clk) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 213 | { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 214 | unsigned long sys_clk; |
| 215 | unsigned long clk_div; |
| 216 | u16 clk_ctl = 0; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 217 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 218 | clk_ctl = bfin_read_SDH_CLK_CTL(); |
| 219 | if (clk) { |
| 220 | /* setting SD_CLK */ |
| 221 | sys_clk = get_sclk(); |
| 222 | bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); |
| 223 | if (sys_clk % (2 * clk) == 0) |
| 224 | clk_div = sys_clk / (2 * clk) - 1; |
| 225 | else |
| 226 | clk_div = sys_clk / (2 * clk); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 227 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 228 | if (clk_div > 0xff) |
| 229 | clk_div = 0xff; |
| 230 | clk_ctl |= (clk_div & 0xff); |
| 231 | clk_ctl |= CLK_E; |
| 232 | bfin_write_SDH_CLK_CTL(clk_ctl); |
| 233 | } else |
| 234 | bfin_write_SDH_CLK_CTL(clk_ctl & ~CLK_E); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 235 | } |
| 236 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 237 | static void bfin_sdh_set_ios(struct mmc *mmc) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 238 | { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 239 | u16 cfg = 0; |
| 240 | u16 clk_ctl = 0; |
| 241 | |
Tom Rini | 0b2da7e | 2014-03-28 16:55:29 -0400 | [diff] [blame] | 242 | if (mmc->bus_width == 4) { |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 243 | cfg = bfin_read_SDH_CFG(); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 244 | #ifndef RSI_BLKSZ |
| 245 | cfg &= ~PD_SDDAT3; |
| 246 | #endif |
| 247 | cfg |= PUP_SDDAT3; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 248 | bfin_write_SDH_CFG(cfg); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 249 | clk_ctl |= WIDE_BUS_4; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 250 | } |
| 251 | bfin_write_SDH_CLK_CTL(clk_ctl); |
| 252 | sdh_set_clk(mmc->clock); |
| 253 | } |
| 254 | |
| 255 | static int bfin_sdh_init(struct mmc *mmc) |
| 256 | { |
Mike Frysinger | a87589f | 2010-06-02 05:59:50 -0400 | [diff] [blame] | 257 | const unsigned short pins[] = PORTMUX_PINS; |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 258 | int ret; |
Mike Frysinger | a87589f | 2010-06-02 05:59:50 -0400 | [diff] [blame] | 259 | |
| 260 | /* Initialize sdh controller */ |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 261 | ret = peripheral_request_list(pins, "bfin_sdh"); |
| 262 | if (ret < 0) |
| 263 | return ret; |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 264 | #if defined(__ADSPBF54x__) |
| 265 | bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1); |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 266 | #endif |
| 267 | bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN); |
| 268 | /* Disable card detect pin */ |
| 269 | bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60); |
Sonic Zhang | 187f32f | 2012-08-16 11:26:00 +0800 | [diff] [blame] | 270 | #ifndef RSI_BLKSZ |
| 271 | bfin_write_SDH_PWR_CTL(PWR_ON | ROD_CTL); |
| 272 | #else |
| 273 | bfin_write_SDH_CFG(bfin_read_SDH_CFG() | PWR_ON); |
| 274 | #endif |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 275 | return 0; |
| 276 | } |
| 277 | |
Pantelis Antoniou | ab769f2 | 2014-02-26 19:28:45 +0200 | [diff] [blame] | 278 | static const struct mmc_ops bfin_mmc_ops = { |
| 279 | .send_cmd = bfin_sdh_request, |
| 280 | .set_ios = bfin_sdh_set_ios, |
| 281 | .init = bfin_sdh_init, |
| 282 | }; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 283 | |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 284 | static struct mmc_config bfin_mmc_cfg = { |
| 285 | .name = "Blackfin SDH", |
| 286 | .ops = &bfin_mmc_ops, |
| 287 | .host_caps = MMC_MODE_4BIT, |
| 288 | .voltages = MMC_VDD_32_33 | MMC_VDD_33_34, |
| 289 | .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT, |
| 290 | }; |
| 291 | |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 292 | int bfin_mmc_init(bd_t *bis) |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 293 | { |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 294 | struct mmc *mmc; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 295 | |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 296 | bfin_mmc_cfg.f_max = get_sclk(); |
| 297 | bfin_mmc_cfg.f_min = bfin_mmc_cfg.f_max >> 9; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 298 | |
Pantelis Antoniou | 93bfd61 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 299 | mmc = mmc_create(&bfin_mmc_cfg, NULL); |
| 300 | if (mmc == NULL) |
| 301 | return -1; |
Cliff Cai | e54c820 | 2009-11-20 08:24:43 +0000 | [diff] [blame] | 302 | |
Cliff Cai | 716ebf4 | 2008-11-29 18:22:38 -0500 | [diff] [blame] | 303 | return 0; |
| 304 | } |