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wdenkb573bf12002-07-16 18:49:25 +00001/*------------------------------------------------------------------------------+
2 *
3 * This source code has been made available to you by IBM on an AS-IS
4 * basis. Anyone receiving this source is licensed under IBM
5 * copyrights to use it in any way he or she deems fit, including
6 * copying it, modifying it, compiling it, and redistributing it either
7 * with or without modifications. No license under IBM patents or
8 * patent applications is to be implied by the copyright license.
9 *
10 * Any user of this software should understand that IBM cannot provide
11 * technical support for this software and will not be responsible for
12 * any consequences resulting from the use of this software.
13 *
14 * Any person who transfers this source code or any derivative work
15 * must include the IBM copyright notice, this paragraph, and the
16 * preceding two paragraphs in the transferred software.
17 *
18 * COPYRIGHT I B M CORPORATION 1995
19 * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 *-------------------------------------------------------------------------------*/
21
22/*-----------------------------------------------------------------------------
23 * Function: ext_bus_cntlr_init
24 * Description: Initializes the External Bus Controller for the external
25 * peripherals. IMPORTANT: For pass1 this code must run from
26 * cache since you can not reliably change a peripheral banks
27 * timing register (pbxap) while running code from that bank.
28 * For ex., since we are running from ROM on bank 0, we can NOT
29 * execute the code that modifies bank 0 timings from ROM, so
30 * we run it from cache.
31 * Bank 0 - Flash or Multi Purpose Socket
32 * Bank 1 - Multi Purpose Socket or Flash
33 * Bank 2 - not used
34 * Bank 3 - not used
35 * Bank 4 - not used
36 * Bank 5 - not used
37 * Bank 6 - used to switch on the 12V for the Multipurpose socket
38 * Bank 7 - Config Register
39 *-----------------------------------------------------------------------------*/
40#include <ppc4xx.h>
41
42#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
43
44#include "configs/PIP405.h"
45#include <ppc_asm.tmpl>
46#include <ppc_defs.h>
47
48#include <asm/cache.h>
49#include <asm/mmu.h>
50
51
52 .globl ext_bus_cntlr_init
53ext_bus_cntlr_init:
54 mflr r4 /* save link register */
55 bl ..getAddr
56..getAddr:
57 mflr r3 /* get address of ..getAddr */
58 mtlr r4 /* restore link register */
59 addi r4,0,14 /* set ctr to 14; used to prefetch */
60 mtctr r4 /* 14 cache lines to fit this function */
61 /* in cache (gives us 8x14=112 instrctns) */
62..ebcloop:
63 icbt r0,r3 /* prefetch cache line for addr in r3 */
64 addi r3,r3,32 /* move to next cache line */
65 bdnz ..ebcloop /* continue for 14 cache lines */
66
67 /*-------------------------------------------------------------------
68 * Delay to ensure all accesses to ROM are complete before changing
69 * bank 0 timings.
70 *------------------------------------------------------------------- */
71 addis r3,0,0x0
72 ori r3,r3,0xA000
73 mtctr r3
74..spinlp:
75 bdnz ..spinlp /* spin loop */
76
77 /*-----------------------------------------------------------------------
78 * decide boot up mode
79 *----------------------------------------------------------------------- */
80 addi r4,0,pb0cr
81 mtdcr ebccfga,r4
82 mfdcr r4,ebccfgd
83
84 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
85 beq 0f /* jump if 8 bit bus width */
86
87 /* setup 16 bit things
88 *-----------------------------------------------------------------------
89 * Memory Bank 0 (16 Bit Flash) initialization
90 *---------------------------------------------------------------------- */
91
92 addi r4,0,pb0ap
93 mtdcr ebccfga,r4
94 addis r4,0,0x9B01
95 ori r4,r4,0x5480
96 mtdcr ebccfgd,r4
97
98 addi r4,0,pb0cr
99 mtdcr ebccfga,r4
100 /* BS=0x011(8MB),BU=0x3(R/W), */
101 addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
102 ori r4,r4,0xA000 /* BW=0x01(16 bits) */
103 mtdcr ebccfgd,r4
104
105 /*-----------------------------------------------------------------------
106 * Memory Bank 1 (Multi Purpose Socket) initialization
107 *----------------------------------------------------------------------*/
108 addi r4,0,pb1ap
109 mtdcr ebccfga,r4
110 addis r4,0,0x0281
111 ori r4,r4,0x5480
112 mtdcr ebccfgd,r4
113
114 addi r4,0,pb1cr
115 mtdcr ebccfga,r4
116 /* BS=0x011(8MB),BU=0x3(R/W), */
117 addis r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
118 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
119 mtdcr ebccfgd,r4
120 b 1f
121
1220:
123 /* 8Bit boot mode: */
124 /*-----------------------------------------------------------------------
125 * Memory Bank 0 Multi Purpose Socket initialization
126 *----------------------------------------------------------------------- */
127
128 addi r4,0,pb0ap
129 mtdcr ebccfga,r4
130 addis r4,0,0x9B01
131 ori r4,r4,0x5480
132 mtdcr ebccfgd,r4
133
134 addi r4,0,pb0cr
135 mtdcr ebccfga,r4
136 /* BS=0x011(4MB),BU=0x3(R/W), */
137 addis r4,0,((FLASH_BASE0_PRELIM & 0xFFF00000) | 0x00050000)@h
138 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
139 mtdcr ebccfgd,r4
140
141 /*-----------------------------------------------------------------------
142 * Memory Bank 1 (Flash) initialization
143 *-----------------------------------------------------------------------*/
144 addi r4,0,pb1ap
145 mtdcr ebccfga,r4
146 addis r4,0,0x0281
147 ori r4,r4,0x5480
148 mtdcr ebccfgd,r4
149
150 addi r4,0,pb1cr
151 mtdcr ebccfga,r4
152 /* BS=0x011(8MB),BU=0x3(R/W), */
153 addis r4,0,((MULTI_PURPOSE_SOCKET_ADDR & 0xFFF00000) | 0x00050000)@h
154 ori r4,r4,0xA000 /* BW=0x0( 8 bits) */
155 mtdcr ebccfgd,r4
156
1571:
158 /*-----------------------------------------------------------------------
159 * Memory Bank 2-3-4-5-6 (not used) initialization
160 *-----------------------------------------------------------------------*/
161 addi r4,0,pb2cr
162 mtdcr ebccfga,r4
163 addis r4,0,0x0000
164 ori r4,r4,0x0000
165 mtdcr ebccfgd,r4
166
167 addi r4,0,pb3cr
168 mtdcr ebccfga,r4
169 addis r4,0,0x0000
170 ori r4,r4,0x0000
171 mtdcr ebccfgd,r4
172
173 addi r4,0,pb4cr
174 mtdcr ebccfga,r4
175 addis r4,0,0x0000
176 ori r4,r4,0x0000
177 mtdcr ebccfgd,r4
178
179 addi r4,0,pb5cr
180 mtdcr ebccfga,r4
181 addis r4,0,0x0000
182 ori r4,r4,0x0000
183 mtdcr ebccfgd,r4
184
185 addi r4,0,pb6cr
186 mtdcr ebccfga,r4
187 addis r4,0,0x0000
188 ori r4,r4,0x0000
189 mtdcr ebccfgd,r4
190
191 /*-----------------------------------------------------------------------
192 * Memory Bank 7 (Config Register) initialization
193 *----------------------------------------------------------------------- */
194 addi r4,0,pb7ap
195 mtdcr ebccfga,r4
196 addis r4,0,0x0181 /* Doc says TWT=3 and Openios TWT=3!! */
197 ori r4,r4,0x5280 /* disable Ready, BEM=0 */
198 mtdcr ebccfgd,r4
199
200 addi r4,0,pb7cr
201 mtdcr ebccfga,r4
202 /* BS=0x0(1MB),BU=0x3(R/W), */
203 addis r4,0,((CONFIG_PORT_ADDR & 0xFFF00000) | 0x00010000)@h
204 ori r4,r4,0x8000 /* BW=0x0(8 bits) */
205 mtdcr ebccfgd,r4
206 nop /* pass2 DCR errata #8 */
207 blr
208
209/*-----------------------------------------------------------------------------
210 * Function: sdram_init
211 * Description: Configures the internal SRAM memory. and setup the
212 * Stackpointer in it.
213 *----------------------------------------------------------------------------- */
214 .globl sdram_init
215
216sdram_init:
217
218
219 blr
220