blob: d2e15491a3d68d631e568769df4c6223409d0a11 [file] [log] [blame]
Simon Glassb4d00b22020-02-06 09:54:53 -07001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 Google LLC
4 * Written by Simon Glass <sjg@chromium.org>
5 */
6
7#include <common.h>
8#include <dm.h>
9#include <clk-uclass.h>
10#include <dt-bindings/clock/intel-clock.h>
11
12static ulong intel_clk_get_rate(struct clk *clk)
13{
14 ulong rate;
15
16 switch (clk->id) {
17 case CLK_I2C:
18 /* Hard-coded to 133MHz on current platforms */
19 return 133333333;
20 default:
21 return -ENODEV;
22 }
23
24 return rate;
25}
26
27static struct clk_ops intel_clk_ops = {
28 .get_rate = intel_clk_get_rate,
29};
30
31static const struct udevice_id intel_clk_ids[] = {
32 { .compatible = "intel,apl-clk" },
33 { }
34};
35
36U_BOOT_DRIVER(clk_intel) = {
37 .name = "clk_intel",
38 .id = UCLASS_CLK,
39 .of_match = intel_clk_ids,
40 .ops = &intel_clk_ops,
41};