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Wenyou Yang2c4b2dd2016-07-25 17:46:17 +08001#include "skeleton.dtsi"
2
3/ {
4 model = "Atmel SAMA5D2 family SoC";
5 compatible = "atmel,sama5d2";
6
7 aliases {
8 spi0 = &spi0;
9 spi1 = &qspi0;
Eugen Hristev58581052019-08-26 06:47:03 +000010 spi2 = &qspi1;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080011 i2c0 = &i2c0;
12 i2c1 = &i2c1;
13 };
14
15 clocks {
16 slow_xtal: slow_xtal {
17 compatible = "fixed-clock";
18 #clock-cells = <0>;
19 clock-frequency = <0>;
20 };
21
22 main_xtal: main_xtal {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
26 };
27 };
28
29 ahb {
30 compatible = "simple-bus";
31 #address-cells = <1>;
32 #size-cells = <1>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080033 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080034
35 usb1: ohci@00400000 {
36 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
37 reg = <0x00400000 0x100000>;
38 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
39 clock-names = "ohci_clk", "hclk", "uhpck";
40 status = "disabled";
41 };
42
43 usb2: ehci@00500000 {
44 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
45 reg = <0x00500000 0x100000>;
46 clocks = <&utmi>, <&uhphs_clk>;
47 clock-names = "usb_clk", "ehci_clk";
48 status = "disabled";
49 };
50
51 sdmmc0: sdio-host@a0000000 {
52 compatible = "atmel,sama5d2-sdhci";
53 reg = <0xa0000000 0x300>;
54 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
55 clock-names = "hclock", "multclk", "baseclk";
56 status = "disabled";
57 };
58
59 sdmmc1: sdio-host@b0000000 {
60 compatible = "atmel,sama5d2-sdhci";
61 reg = <0xb0000000 0x300>;
62 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
63 clock-names = "hclock", "multclk", "baseclk";
64 status = "disabled";
65 };
66
67 apb {
68 compatible = "simple-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080071 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080072
Wenyou Yangd2cd09b2017-09-18 15:25:57 +080073 hlcdc: hlcdc@f0000000 {
74 compatible = "atmel,at91sam9x5-hlcdc";
75 reg = <0xf0000000 0x2000>;
76 clocks = <&lcdc_clk>;
77 status = "disabled";
78 };
79
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080080 pmc: pmc@f0014000 {
81 compatible = "atmel,sama5d2-pmc", "syscon";
82 reg = <0xf0014000 0x160>;
83 #address-cells = <1>;
84 #size-cells = <0>;
85 #interrupt-cells = <1>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080086 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080087
88 main: mainck {
89 compatible = "atmel,at91sam9x5-clk-main";
90 #clock-cells = <0>;
Wenyou Yang4529ee32017-03-23 14:26:23 +080091 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080092 };
93
Wenyou Yang9e63c492016-09-18 15:37:47 +080094 plla: pllack@0 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +080095 compatible = "atmel,sama5d3-clk-pll";
96 #clock-cells = <0>;
97 clocks = <&main>;
98 reg = <0>;
99 atmel,clk-input-range = <12000000 12000000>;
100 #atmel,pll-clk-output-range-cells = <4>;
101 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800102 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800103 };
104
105 plladiv: plladivck {
106 compatible = "atmel,at91sam9x5-clk-plldiv";
107 #clock-cells = <0>;
108 clocks = <&plla>;
109 };
110
111 audio_pll_frac: audiopll_fracck {
112 compatible = "atmel,sama5d2-clk-audio-pll-frac";
113 #clock-cells = <0>;
114 clocks = <&main>;
115 };
116
117 audio_pll_pad: audiopll_padck {
118 compatible = "atmel,sama5d2-clk-audio-pll-pad";
119 #clock-cells = <0>;
120 clocks = <&audio_pll_frac>;
121 };
122
123 audio_pll_pmc: audiopll_pmcck {
124 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
125 #clock-cells = <0>;
126 clocks = <&audio_pll_frac>;
127 };
128
129 utmi: utmick {
130 compatible = "atmel,at91sam9x5-clk-utmi";
131 #clock-cells = <0>;
132 clocks = <&main>;
Wenyou Yang56246d12017-09-05 18:30:08 +0800133 regmap-sfr = <&sfr>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800134 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800135 };
136
137 mck: masterck {
138 compatible = "atmel,at91sam9x5-clk-master";
139 #clock-cells = <0>;
140 clocks = <&main>, <&plladiv>, <&utmi>;
141 atmel,clk-output-range = <124000000 166000000>;
142 atmel,clk-divisors = <1 2 4 3>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800143 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800144 };
145
146 h32ck: h32mxck {
147 #clock-cells = <0>;
148 compatible = "atmel,sama5d4-clk-h32mx";
149 clocks = <&mck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800150 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800151 };
152
153 usb: usbck {
154 compatible = "atmel,at91sam9x5-clk-usb";
155 #clock-cells = <0>;
156 clocks = <&plladiv>, <&utmi>;
157 };
158
159 prog: progck {
160 compatible = "atmel,at91sam9x5-clk-programmable";
161 #address-cells = <1>;
162 #size-cells = <0>;
163 interrupt-parent = <&pmc>;
164 clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
165
Wenyou Yang9e63c492016-09-18 15:37:47 +0800166 prog0: prog@0 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800167 #clock-cells = <0>;
168 reg = <0>;
169 };
170
Wenyou Yang9e63c492016-09-18 15:37:47 +0800171 prog1: prog@1 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800172 #clock-cells = <0>;
173 reg = <1>;
174 };
175
Wenyou Yang9e63c492016-09-18 15:37:47 +0800176 prog2: prog@2 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800177 #clock-cells = <0>;
178 reg = <2>;
179 };
180 };
181
182 systemck {
183 compatible = "atmel,at91rm9200-clk-system";
184 #address-cells = <1>;
185 #size-cells = <0>;
186
Wenyou Yang9e63c492016-09-18 15:37:47 +0800187 ddrck: ddrck@2 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800188 #clock-cells = <0>;
189 reg = <2>;
190 clocks = <&mck>;
191 };
192
Wenyou Yang9e63c492016-09-18 15:37:47 +0800193 lcdck: lcdck@3 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800194 #clock-cells = <0>;
195 reg = <3>;
196 clocks = <&mck>;
197 };
198
Wenyou Yang9e63c492016-09-18 15:37:47 +0800199 uhpck: uhpck@6 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800200 #clock-cells = <0>;
201 reg = <6>;
202 clocks = <&usb>;
203 };
204
Wenyou Yang9e63c492016-09-18 15:37:47 +0800205 udpck: udpck@7 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800206 #clock-cells = <0>;
207 reg = <7>;
208 clocks = <&usb>;
209 };
210
Wenyou Yang9e63c492016-09-18 15:37:47 +0800211 pck0: pck0@8 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800212 #clock-cells = <0>;
213 reg = <8>;
214 clocks = <&prog0>;
215 };
216
Wenyou Yang9e63c492016-09-18 15:37:47 +0800217 pck1: pck1@9 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800218 #clock-cells = <0>;
219 reg = <9>;
220 clocks = <&prog1>;
221 };
222
Wenyou Yang9e63c492016-09-18 15:37:47 +0800223 pck2: pck2@10 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800224 #clock-cells = <0>;
225 reg = <10>;
226 clocks = <&prog2>;
227 };
228
Wenyou Yang9e63c492016-09-18 15:37:47 +0800229 iscck: iscck@18 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800230 #clock-cells = <0>;
231 reg = <18>;
232 clocks = <&mck>;
233 };
234 };
235
236 periph32ck {
237 compatible = "atmel,at91sam9x5-clk-peripheral";
238 #address-cells = <1>;
239 #size-cells = <0>;
240 clocks = <&h32ck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800241 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800242
Wenyou Yang9e63c492016-09-18 15:37:47 +0800243 macb0_clk: macb0_clk@5 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800244 #clock-cells = <0>;
245 reg = <5>;
246 atmel,clk-output-range = <0 83000000>;
247 };
248
Wenyou Yang9e63c492016-09-18 15:37:47 +0800249 tdes_clk: tdes_clk@11 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800250 #clock-cells = <0>;
251 reg = <11>;
252 atmel,clk-output-range = <0 83000000>;
253 };
254
Wenyou Yang9e63c492016-09-18 15:37:47 +0800255 matrix1_clk: matrix1_clk@14 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800256 #clock-cells = <0>;
257 reg = <14>;
258 };
259
Wenyou Yang9e63c492016-09-18 15:37:47 +0800260 hsmc_clk: hsmc_clk@17 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800261 #clock-cells = <0>;
262 reg = <17>;
263 };
264
Wenyou Yang9e63c492016-09-18 15:37:47 +0800265 pioA_clk: pioA_clk@18 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800266 #clock-cells = <0>;
267 reg = <18>;
268 atmel,clk-output-range = <0 83000000>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800269 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800270 };
271
Wenyou Yang9e63c492016-09-18 15:37:47 +0800272 flx0_clk: flx0_clk@19 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800273 #clock-cells = <0>;
274 reg = <19>;
275 atmel,clk-output-range = <0 83000000>;
276 };
277
Wenyou Yang9e63c492016-09-18 15:37:47 +0800278 flx1_clk: flx1_clk@20 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800279 #clock-cells = <0>;
280 reg = <20>;
281 atmel,clk-output-range = <0 83000000>;
282 };
283
Wenyou Yang9e63c492016-09-18 15:37:47 +0800284 flx2_clk: flx2_clk@21 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800285 #clock-cells = <0>;
286 reg = <21>;
287 atmel,clk-output-range = <0 83000000>;
288 };
289
Wenyou Yang9e63c492016-09-18 15:37:47 +0800290 flx3_clk: flx3_clk@22 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800291 #clock-cells = <0>;
292 reg = <22>;
293 atmel,clk-output-range = <0 83000000>;
294 };
295
Wenyou Yang9e63c492016-09-18 15:37:47 +0800296 flx4_clk: flx4_clk@23 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800297 #clock-cells = <0>;
298 reg = <23>;
299 atmel,clk-output-range = <0 83000000>;
300 };
301
Wenyou Yang9e63c492016-09-18 15:37:47 +0800302 uart0_clk: uart0_clk@24 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800303 #clock-cells = <0>;
304 reg = <24>;
305 atmel,clk-output-range = <0 83000000>;
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800306 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800307 };
308
Wenyou Yang9e63c492016-09-18 15:37:47 +0800309 uart1_clk: uart1_clk@25 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800310 #clock-cells = <0>;
311 reg = <25>;
312 atmel,clk-output-range = <0 83000000>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800313 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800314 };
315
Wenyou Yang9e63c492016-09-18 15:37:47 +0800316 uart2_clk: uart2_clk@26 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800317 #clock-cells = <0>;
318 reg = <26>;
319 atmel,clk-output-range = <0 83000000>;
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800320 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800321 };
322
Wenyou Yang9e63c492016-09-18 15:37:47 +0800323 uart3_clk: uart3_clk@27 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800324 #clock-cells = <0>;
325 reg = <27>;
326 atmel,clk-output-range = <0 83000000>;
327 };
328
Wenyou Yang9e63c492016-09-18 15:37:47 +0800329 uart4_clk: uart4_clk@28 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800330 #clock-cells = <0>;
331 reg = <28>;
332 atmel,clk-output-range = <0 83000000>;
333 };
334
Wenyou Yang9e63c492016-09-18 15:37:47 +0800335 twi0_clk: twi0_clk@29 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800336 reg = <29>;
337 #clock-cells = <0>;
338 atmel,clk-output-range = <0 83000000>;
339 };
340
Wenyou Yang9e63c492016-09-18 15:37:47 +0800341 twi1_clk: twi1_clk@30 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800342 #clock-cells = <0>;
343 reg = <30>;
344 atmel,clk-output-range = <0 83000000>;
345 };
346
Wenyou Yang9e63c492016-09-18 15:37:47 +0800347 spi0_clk: spi0_clk@33 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800348 #clock-cells = <0>;
349 reg = <33>;
350 atmel,clk-output-range = <0 83000000>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800351 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800352 };
353
Wenyou Yang9e63c492016-09-18 15:37:47 +0800354 spi1_clk: spi1_clk@34 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800355 #clock-cells = <0>;
356 reg = <34>;
357 atmel,clk-output-range = <0 83000000>;
358 };
359
Wenyou Yang9e63c492016-09-18 15:37:47 +0800360 tcb0_clk: tcb0_clk@35 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800361 #clock-cells = <0>;
362 reg = <35>;
363 atmel,clk-output-range = <0 83000000>;
364 };
365
Wenyou Yang9e63c492016-09-18 15:37:47 +0800366 tcb1_clk: tcb1_clk@36 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800367 #clock-cells = <0>;
368 reg = <36>;
369 atmel,clk-output-range = <0 83000000>;
370 };
371
Wenyou Yang9e63c492016-09-18 15:37:47 +0800372 pwm_clk: pwm_clk@38 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800373 #clock-cells = <0>;
374 reg = <38>;
375 atmel,clk-output-range = <0 83000000>;
376 };
377
Wenyou Yang9e63c492016-09-18 15:37:47 +0800378 adc_clk: adc_clk@40 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800379 #clock-cells = <0>;
380 reg = <40>;
381 atmel,clk-output-range = <0 83000000>;
382 };
383
Wenyou Yang9e63c492016-09-18 15:37:47 +0800384 uhphs_clk: uhphs_clk@41 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800385 #clock-cells = <0>;
386 reg = <41>;
387 atmel,clk-output-range = <0 83000000>;
388 };
389
Wenyou Yang9e63c492016-09-18 15:37:47 +0800390 udphs_clk: udphs_clk@42 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800391 #clock-cells = <0>;
392 reg = <42>;
393 atmel,clk-output-range = <0 83000000>;
394 };
395
Wenyou Yang9e63c492016-09-18 15:37:47 +0800396 ssc0_clk: ssc0_clk@43 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800397 #clock-cells = <0>;
398 reg = <43>;
399 atmel,clk-output-range = <0 83000000>;
400 };
401
Wenyou Yang9e63c492016-09-18 15:37:47 +0800402 ssc1_clk: ssc1_clk@44 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800403 #clock-cells = <0>;
404 reg = <44>;
405 atmel,clk-output-range = <0 83000000>;
406 };
407
Wenyou Yang9e63c492016-09-18 15:37:47 +0800408 trng_clk: trng_clk@47 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800409 #clock-cells = <0>;
410 reg = <47>;
411 atmel,clk-output-range = <0 83000000>;
412 };
413
Wenyou Yang9e63c492016-09-18 15:37:47 +0800414 pdmic_clk: pdmic_clk@48 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800415 #clock-cells = <0>;
416 reg = <48>;
417 atmel,clk-output-range = <0 83000000>;
418 };
419
Wenyou Yang9e63c492016-09-18 15:37:47 +0800420 i2s0_clk: i2s0_clk@54 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800421 #clock-cells = <0>;
422 reg = <54>;
423 atmel,clk-output-range = <0 83000000>;
424 };
425
Wenyou Yang9e63c492016-09-18 15:37:47 +0800426 i2s1_clk: i2s1_clk@55 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800427 #clock-cells = <0>;
428 reg = <55>;
429 atmel,clk-output-range = <0 83000000>;
430 };
431
Wenyou Yang9e63c492016-09-18 15:37:47 +0800432 can0_clk: can0_clk@56 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800433 #clock-cells = <0>;
434 reg = <56>;
435 atmel,clk-output-range = <0 83000000>;
436 };
437
Wenyou Yang9e63c492016-09-18 15:37:47 +0800438 can1_clk: can1_clk@57 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800439 #clock-cells = <0>;
440 reg = <57>;
441 atmel,clk-output-range = <0 83000000>;
442 };
443
Wenyou Yang9e63c492016-09-18 15:37:47 +0800444 classd_clk: classd_clk@59 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800445 #clock-cells = <0>;
446 reg = <59>;
447 atmel,clk-output-range = <0 83000000>;
448 };
449 };
450
451 periph64ck {
452 compatible = "atmel,at91sam9x5-clk-peripheral";
453 #address-cells = <1>;
454 #size-cells = <0>;
455 clocks = <&mck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800456 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800457
Wenyou Yang9e63c492016-09-18 15:37:47 +0800458 dma0_clk: dma0_clk@6 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800459 #clock-cells = <0>;
460 reg = <6>;
461 };
462
Wenyou Yang9e63c492016-09-18 15:37:47 +0800463 dma1_clk: dma1_clk@7 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800464 #clock-cells = <0>;
465 reg = <7>;
466 };
467
Wenyou Yang9e63c492016-09-18 15:37:47 +0800468 aes_clk: aes_clk@9 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800469 #clock-cells = <0>;
470 reg = <9>;
471 };
472
Wenyou Yang9e63c492016-09-18 15:37:47 +0800473 aesb_clk: aesb_clk@10 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800474 #clock-cells = <0>;
475 reg = <10>;
476 };
477
Wenyou Yang9e63c492016-09-18 15:37:47 +0800478 sha_clk: sha_clk@12 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800479 #clock-cells = <0>;
480 reg = <12>;
481 };
482
Wenyou Yang9e63c492016-09-18 15:37:47 +0800483 mpddr_clk: mpddr_clk@13 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800484 #clock-cells = <0>;
485 reg = <13>;
486 };
487
Wenyou Yang9e63c492016-09-18 15:37:47 +0800488 matrix0_clk: matrix0_clk@15 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800489 #clock-cells = <0>;
490 reg = <15>;
491 };
492
Wenyou Yang9e63c492016-09-18 15:37:47 +0800493 sdmmc0_hclk: sdmmc0_hclk@31 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800494 #clock-cells = <0>;
495 reg = <31>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800496 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800497 };
498
Wenyou Yang9e63c492016-09-18 15:37:47 +0800499 sdmmc1_hclk: sdmmc1_hclk@32 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800500 #clock-cells = <0>;
501 reg = <32>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800502 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800503 };
504
Wenyou Yang9e63c492016-09-18 15:37:47 +0800505 lcdc_clk: lcdc_clk@45 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800506 #clock-cells = <0>;
507 reg = <45>;
508 };
509
Wenyou Yang9e63c492016-09-18 15:37:47 +0800510 isc_clk: isc_clk@46 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800511 #clock-cells = <0>;
512 reg = <46>;
513 };
514
Wenyou Yang9e63c492016-09-18 15:37:47 +0800515 qspi0_clk: qspi0_clk@52 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800516 #clock-cells = <0>;
517 reg = <52>;
Wenyou Yangce4054b2017-09-13 14:58:54 +0800518 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800519 };
520
Wenyou Yang9e63c492016-09-18 15:37:47 +0800521 qspi1_clk: qspi1_clk@53 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800522 #clock-cells = <0>;
523 reg = <53>;
Wenyou Yangce4054b2017-09-13 14:58:54 +0800524 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800525 };
526 };
527
528 gck {
529 compatible = "atmel,sama5d2-clk-generated";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 interrupt-parent = <&pmc>;
533 clocks = <&main>, <&plla>, <&utmi>, <&mck>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800534 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800535
Wenyou Yang9e63c492016-09-18 15:37:47 +0800536 sdmmc0_gclk: sdmmc0_gclk@31 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800537 #clock-cells = <0>;
538 reg = <31>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800539 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800540 };
541
Wenyou Yang9e63c492016-09-18 15:37:47 +0800542 sdmmc1_gclk: sdmmc1_gclk@32 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800543 #clock-cells = <0>;
544 reg = <32>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800545 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800546 };
547
Wenyou Yang9e63c492016-09-18 15:37:47 +0800548 tcb0_gclk: tcb0_gclk@35 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800549 #clock-cells = <0>;
550 reg = <35>;
551 atmel,clk-output-range = <0 83000000>;
552 };
553
Wenyou Yang9e63c492016-09-18 15:37:47 +0800554 tcb1_gclk: tcb1_gclk@36 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800555 #clock-cells = <0>;
556 reg = <36>;
557 atmel,clk-output-range = <0 83000000>;
558 };
559
Wenyou Yang9e63c492016-09-18 15:37:47 +0800560 pwm_gclk: pwm_gclk@38 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800561 #clock-cells = <0>;
562 reg = <38>;
563 atmel,clk-output-range = <0 83000000>;
564 };
565
Wenyou Yang9e63c492016-09-18 15:37:47 +0800566 pdmic_gclk: pdmic_gclk@48 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800567 #clock-cells = <0>;
568 reg = <48>;
569 };
570
Wenyou Yang9e63c492016-09-18 15:37:47 +0800571 i2s0_gclk: i2s0_gclk@54 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800572 #clock-cells = <0>;
573 reg = <54>;
574 };
575
Wenyou Yang9e63c492016-09-18 15:37:47 +0800576 i2s1_gclk: i2s1_gclk@55 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800577 #clock-cells = <0>;
578 reg = <55>;
579 };
580
Wenyou Yang9e63c492016-09-18 15:37:47 +0800581 can0_gclk: can0_gclk@56 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800582 #clock-cells = <0>;
583 reg = <56>;
584 atmel,clk-output-range = <0 80000000>;
585 };
586
Wenyou Yang9e63c492016-09-18 15:37:47 +0800587 can1_gclk: can1_gclk@57 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800588 #clock-cells = <0>;
589 reg = <57>;
590 atmel,clk-output-range = <0 80000000>;
591 };
592
Wenyou Yang9e63c492016-09-18 15:37:47 +0800593 classd_gclk: classd_gclk@59 {
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800594 #clock-cells = <0>;
595 reg = <59>;
596 atmel,clk-output-range = <0 100000000>;
597 };
598 };
599 };
600
601 qspi0: spi@f0020000 {
602 compatible = "atmel,sama5d2-qspi";
603 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
604 reg-names = "qspi_base", "qspi_mmap";
605 #address-cells = <1>;
606 #size-cells = <0>;
607 clocks = <&qspi0_clk>;
608 status = "disabled";
609 };
610
Wenyou Yangce4054b2017-09-13 14:58:54 +0800611 qspi1: spi@f0024000 {
612 compatible = "atmel,sama5d2-qspi";
613 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
614 reg-names = "qspi_base", "qspi_mmap";
615 #address-cells = <1>;
616 #size-cells = <0>;
617 clocks = <&qspi1_clk>;
618 status = "disabled";
619 };
620
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800621 spi0: spi@f8000000 {
622 compatible = "atmel,at91rm9200-spi";
623 reg = <0xf8000000 0x100>;
624 clocks = <&spi0_clk>;
625 clock-names = "spi_clk";
626 #address-cells = <1>;
627 #size-cells = <0>;
628 status = "disabled";
629 };
630
631 macb0: ethernet@f8008000 {
632 compatible = "cdns,macb";
633 reg = <0xf8008000 0x1000>;
634 #address-cells = <1>;
635 #size-cells = <0>;
636 clocks = <&macb0_clk>, <&macb0_clk>;
637 clock-names = "hclk", "pclk";
638 status = "disabled";
639 };
640
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800641 uart0: serial@f801c000 {
642 compatible = "atmel,at91sam9260-usart";
643 reg = <0xf801c000 0x100>;
644 clocks = <&uart0_clk>;
645 clock-names = "usart";
646 status = "disabled";
647 };
648
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800649 uart1: serial@f8020000 {
650 compatible = "atmel,at91sam9260-usart";
651 reg = <0xf8020000 0x100>;
Wenyou Yang20bb1652017-03-23 14:26:22 +0800652 clocks = <&uart1_clk>;
653 clock-names = "usart";
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800654 status = "disabled";
655 };
656
Ludovic Desrochesaaa4ba92017-11-17 14:57:12 +0800657 uart2: serial@f8024000 {
658 compatible = "atmel,at91sam9260-usart";
659 reg = <0xf8024000 0x100>;
660 clocks = <&uart2_clk>;
661 clock-names = "usart";
662 status = "disabled";
663 };
664
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800665 i2c0: i2c@f8028000 {
666 compatible = "atmel,sama5d2-i2c";
667 reg = <0xf8028000 0x100>;
668 #address-cells = <1>;
669 #size-cells = <0>;
670 clocks = <&twi0_clk>;
671 status = "disabled";
672 };
673
Wenyou.Yang@microchip.comfc6adeb2017-08-15 17:40:27 +0800674 rstc@f8048000 {
675 compatible = "atmel,sama5d3-rstc";
676 reg = <0xf8048000 0x10>;
677 clocks = <&clk32k>;
678 };
679
680 shdwc@f8048010 {
681 compatible = "atmel,sama5d2-shdwc";
682 reg = <0xf8048010 0x10>;
683 clocks = <&clk32k>;
684 #address-cells = <1>;
685 #size-cells = <0>;
686 atmel,wakeup-rtc-timer;
687 };
688
689 pit: timer@f8048030 {
690 compatible = "atmel,at91sam9260-pit";
691 reg = <0xf8048030 0x10>;
692 clocks = <&h32ck>;
693 };
694
695 watchdog@f8048040 {
696 compatible = "atmel,sama5d4-wdt";
697 reg = <0xf8048040 0x10>;
698 clocks = <&clk32k>;
699 status = "disabled";
700 };
701
Wenyou Yang56246d12017-09-05 18:30:08 +0800702 sfr: sfr@f8030000 {
703 compatible = "atmel,sama5d2-sfr", "syscon";
704 reg = <0xf8030000 0x98>;
705 };
706
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800707 sckc@f8048050 {
708 compatible = "atmel,at91sam9x5-sckc";
709 reg = <0xf8048050 0x4>;
710
711 slow_rc_osc: slow_rc_osc {
712 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
713 #clock-cells = <0>;
714 clock-frequency = <32768>;
715 clock-accuracy = <250000000>;
716 atmel,startup-time-usec = <75>;
717 };
718
719 slow_osc: slow_osc {
720 compatible = "atmel,at91sam9x5-clk-slow-osc";
721 #clock-cells = <0>;
722 clocks = <&slow_xtal>;
723 atmel,startup-time-usec = <1200000>;
724 };
725
726 clk32k: slowck {
727 compatible = "atmel,at91sam9x5-clk-slow";
728 #clock-cells = <0>;
729 clocks = <&slow_rc_osc &slow_osc>;
730 };
731 };
732
733 spi1: spi@fc000000 {
734 compatible = "atmel,at91rm9200-spi";
735 reg = <0xfc000000 0x100>;
736 #address-cells = <1>;
737 #size-cells = <0>;
738 status = "disabled";
739 };
740
Wenyou Yangce4054b2017-09-13 14:58:54 +0800741 uart3: serial@fc008000 {
742 compatible = "atmel,at91sam9260-usart";
743 reg = <0xfc008000 0x100>;
744 clocks = <&uart3_clk>;
745 clock-names = "usart";
746 status = "disabled";
747 };
748
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800749 i2c1: i2c@fc028000 {
750 compatible = "atmel,sama5d2-i2c";
751 reg = <0xfc028000 0x100>;
752 #address-cells = <1>;
753 #size-cells = <0>;
754 clocks = <&twi1_clk>;
755 status = "disabled";
756 };
757
758 pioA: gpio@fc038000 {
759 compatible = "atmel,sama5d2-gpio";
760 reg = <0xfc038000 0x600>;
761 clocks = <&pioA_clk>;
762 gpio-controller;
763 #gpio-cells = <2>;
Wenyou Yang4529ee32017-03-23 14:26:23 +0800764 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800765
766 pinctrl {
767 compatible = "atmel,sama5d2-pinctrl";
Wenyou Yang4529ee32017-03-23 14:26:23 +0800768 u-boot,dm-pre-reloc;
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800769 };
770 };
771 };
772 };
Eugen Hristev7f0110d2018-09-18 10:35:53 +0300773
774 onewire_tm: onewire {
775 compatible = "w1-gpio";
776 status = "disabled";
777 };
Wenyou Yang2c4b2dd2016-07-25 17:46:17 +0800778};