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Nobuhiro Iwamatsu6d1d5cf2011-11-15 12:29:06 +09001/*
2 * Copyright (C) 2011 Renesas Solutions Corp.
3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
4 *
5 * board/renesas/ecovec/lowlevel_init.S
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu6d1d5cf2011-11-15 12:29:06 +09008 */
9
10#include <config.h>
11#include <version.h>
12#include <asm/processor.h>
13#include <asm/macro.h>
14#include <configs/ecovec.h>
15
16 .global lowlevel_init
17
18 .text
19 .align 2
20
21lowlevel_init:
22
23 /* jump to 0xA0020000 if bit 1 of PVDR_A */
24 mov.l PVDR_A, r1
25 mov.l PVDR_D, r2
26 mov.b @r1, r0
27 tst r0, r2
28 bt 1f
29 mov.l JUMP_A, r1
30 jmp @r1
31 nop
32
331:
34 /* Disable watchdog */
35 write16 RWTCSR_A, RWTCSR_D
36
37 /* MMU Disable */
38 write32 MMUCR_A, MMUCR_D
39
40 /* Setup clocks */
41 write32 PLLCR_A, PLLCR_D
42 write32 FRQCRA_A, FRQCRA_D
43 write32 FRQCRB_A, FRQCRB_D
44
45 wait_timer TIMER_D
46
47 write32 MMSELR_A, MMSELR_D
48
49 /* Srtup BSC */
50 write32 CMNCR_A, CMNCR_D
51 write32 CS0BCR_A, CS0BCR_D
52 write32 CS0WCR_A, CS0WCR_D
53
54 wait_timer TIMER_D
55
56 /* Setup SDRAM */
57 write32 DBPDCNT0_A, DBPDCNT0_D0
58 write32 DBCONF_A, DBCONF_D
59 write32 DBTR0_A, DBTR0_D
60 write32 DBTR1_A, DBTR1_D
61 write32 DBTR2_A, DBTR2_D
62 write32 DBTR3_A, DBTR3_D
63 write32 DBKIND_A, DBKIND_D
64 write32 DBCKECNT_A, DBCKECNT_D
65
66 wait_timer TIMER_D
67
68 write32 DBCMDCNT_A, DBCMDCNT_D0
69 write32 DBMRCNT_A, DBMRCNT_D0
70 write32 DBMRCNT_A, DBMRCNT_D1
71 write32 DBMRCNT_A, DBMRCNT_D2
72 write32 DBMRCNT_A, DBMRCNT_D3
73 write32 DBCMDCNT_A, DBCMDCNT_D0
74 write32 DBCMDCNT_A, DBCMDCNT_D1
75 write32 DBCMDCNT_A, DBCMDCNT_D1
76 write32 DBMRCNT_A, DBMRCNT_D4
77 write32 DBMRCNT_A, DBMRCNT_D5
78 write32 DBMRCNT_A, DBMRCNT_D6
79
80 wait_timer TIMER_D
81
82 write32 DBEN_A, DBEN_D
83 write32 DBRFPDN1_A, DBRFPDN1_D
84 write32 DBRFPDN2_A, DBRFPDN2_D
85 write32 DBCMDCNT_A, DBCMDCNT_D0
86
87
88 /* Dummy read */
89 mov.l DUMMY_A ,r1
90 synco
91 mov.l @r1, r0
92 synco
93
94 mov.l SDRAM_A ,r1
95 synco
96 mov.l @r1, r0
97 synco
98 wait_timer TIMER_D
99
100 add #4, r1
101 synco
102 mov.l @r1, r0
103 synco
104 wait_timer TIMER_D
105
106 add #4, r1
107 synco
108 mov.l @r1, r0
109 synco
110 wait_timer TIMER_D
111
112 add #4, r1
113 synco
114 mov.l @r1, r0
115 synco
116 wait_timer TIMER_D
117
118 write32 DBCMDCNT_A, DBCMDCNT_D0
119 write32 DBCMDCNT_A, DBCMDCNT_D1
120 write32 DBPDCNT0_A, DBPDCNT0_D1
121 write32 DBRFPDN0_A, DBRFPDN0_D
122
123 wait_timer TIMER_D
124
125 write32 CCR_A, CCR_D
126
127 stc sr, r0
128 mov.l SR_MASK_D, r1
129 and r1, r0
130 ldc r0, sr
131
132 rts
133
134 .align 2
135
136PVDR_A: .long PVDR
137PVDR_D: .long 0x00000001
138JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
139TIMER_D: .long 64
140RWTCSR_A: .long RWTCSR
141RWTCSR_D: .long 0x0000A507
142MMUCR_A: .long MMUCR
143MMUCR_D: .long 0x00000004
144PLLCR_A: .long PLLCR
145PLLCR_D: .long 0x00004000
146FRQCRA_A: .long FRQCRA
147FRQCRA_D: .long 0x8E003508
148FRQCRB_A: .long FRQCRB
149FRQCRB_D: .long 0x0
150MMSELR_A: .long MMSELR
151MMSELR_D: .long 0xA5A50000
152CMNCR_A: .long CMNCR
153CMNCR_D: .long 0x00000013
154CS0BCR_A: .long CS0BCR
155CS0BCR_D: .long 0x11110400
156CS0WCR_A: .long CS0WCR
157CS0WCR_D: .long 0x00000440
158DBPDCNT0_A: .long DBPDCNT0
159DBPDCNT0_D0: .long 0x00000181
160DBPDCNT0_D1: .long 0x00000080
161DBCONF_A: .long DBCONF
162DBCONF_D: .long 0x015B0002
163DBTR0_A: .long DBTR0
164DBTR0_D: .long 0x03061502
165DBTR1_A: .long DBTR1
166DBTR1_D: .long 0x02020102
167DBTR2_A: .long DBTR2
168DBTR2_D: .long 0x01090305
169DBTR3_A: .long DBTR3
170DBTR3_D: .long 0x00000002
171DBKIND_A: .long DBKIND
172DBKIND_D: .long 0x00000005
173DBCKECNT_A: .long DBCKECNT
174DBCKECNT_D: .long 0x00000001
175DBCMDCNT_A: .long DBCMDCNT
176DBCMDCNT_D0:.long 0x2
177DBCMDCNT_D1:.long 0x4
178DBMRCNT_A: .long DBMRCNT
179DBMRCNT_D0: .long 0x00020000
180DBMRCNT_D1: .long 0x00030000
181DBMRCNT_D2: .long 0x00010040
182DBMRCNT_D3: .long 0x00000532
183DBMRCNT_D4: .long 0x00000432
184DBMRCNT_D5: .long 0x000103C0
185DBMRCNT_D6: .long 0x00010040
186DBEN_A: .long DBEN
187DBEN_D: .long 0x01
188DBRFPDN0_A: .long DBRFPDN0
189DBRFPDN1_A: .long DBRFPDN1
190DBRFPDN2_A: .long DBRFPDN2
191DBRFPDN0_D: .long 0x00010000
192DBRFPDN1_D: .long 0x00000613
193DBRFPDN2_D: .long 0x238C003A
194SDRAM_A: .long 0xa8000000
195DUMMY_A: .long 0x0c400000
196CCR_A: .long CCR
197CCR_D: .long 0x0000090B
198SR_MASK_D: .long 0xEFFFFF0F