blob: 2d97625fba73b81dcb8a2ba2d55d5e1d5eef0bcb [file] [log] [blame]
Allen Martin77c42e82013-03-16 18:58:13 +00001/*
2 * NVIDIA Tegra SPI controller (T114 and later)
3 *
4 * Copyright (c) 2010-2013 NVIDIA Corporation
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060025#include <dm.h>
Allen Martin77c42e82013-03-16 18:58:13 +000026#include <asm/io.h>
Allen Martin77c42e82013-03-16 18:58:13 +000027#include <asm/arch/clock.h>
28#include <asm/arch-tegra/clk_rst.h>
Allen Martin77c42e82013-03-16 18:58:13 +000029#include <spi.h>
30#include <fdtdec.h>
Simon Glassfda6fac2014-10-13 23:42:13 -060031#include "tegra_spi.h"
Allen Martin77c42e82013-03-16 18:58:13 +000032
33DECLARE_GLOBAL_DATA_PTR;
34
35/* COMMAND1 */
36#define SPI_CMD1_GO (1 << 31)
37#define SPI_CMD1_M_S (1 << 30)
38#define SPI_CMD1_MODE_MASK 0x3
39#define SPI_CMD1_MODE_SHIFT 28
40#define SPI_CMD1_CS_SEL_MASK 0x3
41#define SPI_CMD1_CS_SEL_SHIFT 26
42#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
43#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
44#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
45#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
46#define SPI_CMD1_CS_SW_HW (1 << 21)
47#define SPI_CMD1_CS_SW_VAL (1 << 20)
48#define SPI_CMD1_IDLE_SDA_MASK 0x3
49#define SPI_CMD1_IDLE_SDA_SHIFT 18
50#define SPI_CMD1_BIDIR (1 << 17)
51#define SPI_CMD1_LSBI_FE (1 << 16)
52#define SPI_CMD1_LSBY_FE (1 << 15)
53#define SPI_CMD1_BOTH_EN_BIT (1 << 14)
54#define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
55#define SPI_CMD1_RX_EN (1 << 12)
56#define SPI_CMD1_TX_EN (1 << 11)
57#define SPI_CMD1_PACKED (1 << 5)
58#define SPI_CMD1_BIT_LEN_MASK 0x1F
59#define SPI_CMD1_BIT_LEN_SHIFT 0
60
61/* COMMAND2 */
62#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
63#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
64#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
65#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
66
67/* TRANSFER STATUS */
68#define SPI_XFER_STS_RDY (1 << 30)
69
70/* FIFO STATUS */
71#define SPI_FIFO_STS_CS_INACTIVE (1 << 31)
72#define SPI_FIFO_STS_FRAME_END (1 << 30)
73#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
74#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
75#define SPI_FIFO_STS_ERR (1 << 8)
76#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7)
77#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6)
78#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5)
79#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4)
80#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3)
81#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
82#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1)
83#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
84
85#define SPI_TIMEOUT 1000
86#define TEGRA_SPI_MAX_FREQ 52000000
87
88struct spi_regs {
89 u32 command1; /* 000:SPI_COMMAND1 register */
90 u32 command2; /* 004:SPI_COMMAND2 register */
91 u32 timing1; /* 008:SPI_CS_TIM1 register */
92 u32 timing2; /* 00c:SPI_CS_TIM2 register */
93 u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
94 u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
95 u32 tx_data; /* 018:SPI_TX_DATA register */
96 u32 rx_data; /* 01c:SPI_RX_DATA register */
97 u32 dma_ctl; /* 020:SPI_DMA_CTL register */
98 u32 dma_blk; /* 024:SPI_DMA_BLK register */
99 u32 rsvd[56]; /* 028-107 reserved */
100 u32 tx_fifo; /* 108:SPI_FIFO1 register */
101 u32 rsvd2[31]; /* 10c-187 reserved */
102 u32 rx_fifo; /* 188:SPI_FIFO2 register */
103 u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
104};
105
Simon Glassfda6fac2014-10-13 23:42:13 -0600106struct tegra114_spi_priv {
Allen Martin77c42e82013-03-16 18:58:13 +0000107 struct spi_regs *regs;
108 unsigned int freq;
109 unsigned int mode;
110 int periph_id;
111 int valid;
Simon Glassfda6fac2014-10-13 23:42:13 -0600112 int last_transaction_us;
Allen Martin77c42e82013-03-16 18:58:13 +0000113};
114
Simon Glassfda6fac2014-10-13 23:42:13 -0600115static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000116{
Simon Glassfda6fac2014-10-13 23:42:13 -0600117 struct tegra_spi_platdata *plat = bus->platdata;
118 const void *blob = gd->fdt_blob;
119 int node = bus->of_offset;
120
121 plat->base = fdtdec_get_addr(blob, node, "reg");
122 plat->periph_id = clock_decode_periph_id(blob, node);
123
124 if (plat->periph_id == PERIPH_ID_NONE) {
125 debug("%s: could not decode periph id %d\n", __func__,
126 plat->periph_id);
127 return -FDT_ERR_NOTFOUND;
128 }
129
130 /* Use 500KHz as a suitable default */
131 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
132 500000);
133 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
134 "spi-deactivate-delay", 0);
135 debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
136 __func__, plat->base, plat->periph_id, plat->frequency,
137 plat->deactivate_delay_us);
138
139 return 0;
Allen Martin77c42e82013-03-16 18:58:13 +0000140}
141
Simon Glassfda6fac2014-10-13 23:42:13 -0600142static int tegra114_spi_probe(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000143{
Simon Glassfda6fac2014-10-13 23:42:13 -0600144 struct tegra_spi_platdata *plat = dev_get_platdata(bus);
145 struct tegra114_spi_priv *priv = dev_get_priv(bus);
146
147 priv->regs = (struct spi_regs *)plat->base;
148
149 priv->last_transaction_us = timer_get_us();
150 priv->freq = plat->frequency;
151 priv->periph_id = plat->periph_id;
152
153 return 0;
Allen Martin77c42e82013-03-16 18:58:13 +0000154}
155
Simon Glassfda6fac2014-10-13 23:42:13 -0600156static int tegra114_spi_claim_bus(struct udevice *bus)
Allen Martin77c42e82013-03-16 18:58:13 +0000157{
Simon Glassfda6fac2014-10-13 23:42:13 -0600158 struct tegra114_spi_priv *priv = dev_get_priv(bus);
159 struct spi_regs *regs = priv->regs;
Allen Martin77c42e82013-03-16 18:58:13 +0000160
161 /* Change SPI clock to correct frequency, PLLP_OUT0 source */
Simon Glassfda6fac2014-10-13 23:42:13 -0600162 clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
Allen Martin77c42e82013-03-16 18:58:13 +0000163
164 /* Clear stale status here */
165 setbits_le32(&regs->fifo_status,
166 SPI_FIFO_STS_ERR |
167 SPI_FIFO_STS_TX_FIFO_OVF |
168 SPI_FIFO_STS_TX_FIFO_UNR |
169 SPI_FIFO_STS_RX_FIFO_OVF |
170 SPI_FIFO_STS_RX_FIFO_UNR |
171 SPI_FIFO_STS_TX_FIFO_FULL |
172 SPI_FIFO_STS_TX_FIFO_EMPTY |
173 SPI_FIFO_STS_RX_FIFO_FULL |
174 SPI_FIFO_STS_RX_FIFO_EMPTY);
175 debug("%s: FIFO STATUS = %08x\n", __func__, readl(&regs->fifo_status));
176
177 /* Set master mode and sw controlled CS */
178 setbits_le32(&regs->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
Simon Glassfda6fac2014-10-13 23:42:13 -0600179 (priv->mode << SPI_CMD1_MODE_SHIFT));
Allen Martin77c42e82013-03-16 18:58:13 +0000180 debug("%s: COMMAND1 = %08x\n", __func__, readl(&regs->command1));
181
182 return 0;
183}
184
Simon Glassfda6fac2014-10-13 23:42:13 -0600185/**
186 * Activate the CS by driving it LOW
187 *
188 * @param slave Pointer to spi_slave to which controller has to
189 * communicate with
190 */
191static void spi_cs_activate(struct udevice *dev)
Allen Martin77c42e82013-03-16 18:58:13 +0000192{
Simon Glassfda6fac2014-10-13 23:42:13 -0600193 struct udevice *bus = dev->parent;
194 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
195 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Allen Martin77c42e82013-03-16 18:58:13 +0000196
Simon Glassfda6fac2014-10-13 23:42:13 -0600197 /* If it's too soon to do another transaction, wait */
198 if (pdata->deactivate_delay_us &&
199 priv->last_transaction_us) {
200 ulong delay_us; /* The delay completed so far */
201 delay_us = timer_get_us() - priv->last_transaction_us;
202 if (delay_us < pdata->deactivate_delay_us)
203 udelay(pdata->deactivate_delay_us - delay_us);
204 }
205
206 clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
Allen Martin77c42e82013-03-16 18:58:13 +0000207}
208
Simon Glassfda6fac2014-10-13 23:42:13 -0600209/**
210 * Deactivate the CS by driving it HIGH
211 *
212 * @param slave Pointer to spi_slave to which controller has to
213 * communicate with
214 */
215static void spi_cs_deactivate(struct udevice *dev)
Allen Martin77c42e82013-03-16 18:58:13 +0000216{
Simon Glassfda6fac2014-10-13 23:42:13 -0600217 struct udevice *bus = dev->parent;
218 struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
219 struct tegra114_spi_priv *priv = dev_get_priv(bus);
Allen Martin77c42e82013-03-16 18:58:13 +0000220
Simon Glassfda6fac2014-10-13 23:42:13 -0600221 setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
222
223 /* Remember time of this transaction so we can honour the bus delay */
224 if (pdata->deactivate_delay_us)
225 priv->last_transaction_us = timer_get_us();
226
227 debug("Deactivate CS, bus '%s'\n", bus->name);
Allen Martin77c42e82013-03-16 18:58:13 +0000228}
229
Simon Glassfda6fac2014-10-13 23:42:13 -0600230static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
231 const void *data_out, void *data_in,
232 unsigned long flags)
Allen Martin77c42e82013-03-16 18:58:13 +0000233{
Simon Glassfda6fac2014-10-13 23:42:13 -0600234 struct udevice *bus = dev->parent;
235 struct tegra114_spi_priv *priv = dev_get_priv(bus);
236 struct spi_regs *regs = priv->regs;
Allen Martin77c42e82013-03-16 18:58:13 +0000237 u32 reg, tmpdout, tmpdin = 0;
238 const u8 *dout = data_out;
239 u8 *din = data_in;
240 int num_bytes;
241 int ret;
242
243 debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
Simon Glassfda6fac2014-10-13 23:42:13 -0600244 __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
Allen Martin77c42e82013-03-16 18:58:13 +0000245 if (bitlen % 8)
246 return -1;
247 num_bytes = bitlen / 8;
248
249 ret = 0;
250
251 /* clear all error status bits */
252 reg = readl(&regs->fifo_status);
253 writel(reg, &regs->fifo_status);
254
Allen Martin77c42e82013-03-16 18:58:13 +0000255 clrsetbits_le32(&regs->command1, SPI_CMD1_CS_SW_VAL,
256 SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
Simon Glassfda6fac2014-10-13 23:42:13 -0600257 (spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
Allen Martin77c42e82013-03-16 18:58:13 +0000258
259 /* set xfer size to 1 block (32 bits) */
260 writel(0, &regs->dma_blk);
261
262 if (flags & SPI_XFER_BEGIN)
Simon Glassfda6fac2014-10-13 23:42:13 -0600263 spi_cs_activate(dev);
Allen Martin77c42e82013-03-16 18:58:13 +0000264
265 /* handle data in 32-bit chunks */
266 while (num_bytes > 0) {
267 int bytes;
Allen Martin77c42e82013-03-16 18:58:13 +0000268 int tm, i;
269
270 tmpdout = 0;
271 bytes = (num_bytes > 4) ? 4 : num_bytes;
272
273 if (dout != NULL) {
274 for (i = 0; i < bytes; ++i)
275 tmpdout = (tmpdout << 8) | dout[i];
276 dout += bytes;
277 }
278
279 num_bytes -= bytes;
280
Yen Lin60acde42013-12-18 11:18:46 -0700281 /* clear ready bit */
282 setbits_le32(&regs->xfer_status, SPI_XFER_STS_RDY);
283
Allen Martin77c42e82013-03-16 18:58:13 +0000284 clrsetbits_le32(&regs->command1,
285 SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
286 (bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
287 writel(tmpdout, &regs->tx_fifo);
288 setbits_le32(&regs->command1, SPI_CMD1_GO);
289
290 /*
291 * Wait for SPI transmit FIFO to empty, or to time out.
292 * The RX FIFO status will be read and cleared last
293 */
Yen Lin60acde42013-12-18 11:18:46 -0700294 for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
Allen Martin77c42e82013-03-16 18:58:13 +0000295 u32 fifo_status, xfer_status;
296
Allen Martin77c42e82013-03-16 18:58:13 +0000297 xfer_status = readl(&regs->xfer_status);
298 if (!(xfer_status & SPI_XFER_STS_RDY))
299 continue;
300
Yen Lin60acde42013-12-18 11:18:46 -0700301 fifo_status = readl(&regs->fifo_status);
Allen Martin77c42e82013-03-16 18:58:13 +0000302 if (fifo_status & SPI_FIFO_STS_ERR) {
303 debug("%s: got a fifo error: ", __func__);
304 if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
305 debug("tx FIFO overflow ");
306 if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
307 debug("tx FIFO underrun ");
308 if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
309 debug("rx FIFO overflow ");
310 if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
311 debug("rx FIFO underrun ");
312 if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
313 debug("tx FIFO full ");
314 if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
315 debug("tx FIFO empty ");
316 if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
317 debug("rx FIFO full ");
318 if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
319 debug("rx FIFO empty ");
320 debug("\n");
321 break;
322 }
323
324 if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
325 tmpdin = readl(&regs->rx_fifo);
Allen Martin77c42e82013-03-16 18:58:13 +0000326
327 /* swap bytes read in */
328 if (din != NULL) {
329 for (i = bytes - 1; i >= 0; --i) {
330 din[i] = tmpdin & 0xff;
331 tmpdin >>= 8;
332 }
333 din += bytes;
334 }
Yen Lin60acde42013-12-18 11:18:46 -0700335
336 /* We can exit when we've had both RX and TX */
337 break;
Allen Martin77c42e82013-03-16 18:58:13 +0000338 }
339 }
340
341 if (tm >= SPI_TIMEOUT)
342 ret = tm;
343
344 /* clear ACK RDY, etc. bits */
345 writel(readl(&regs->fifo_status), &regs->fifo_status);
346 }
347
348 if (flags & SPI_XFER_END)
Simon Glassfda6fac2014-10-13 23:42:13 -0600349 spi_cs_deactivate(dev);
Allen Martin77c42e82013-03-16 18:58:13 +0000350
351 debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
352 __func__, tmpdin, readl(&regs->fifo_status));
353
354 if (ret) {
355 printf("%s: timeout during SPI transfer, tm %d\n",
356 __func__, ret);
357 return -1;
358 }
359
Simon Glassfda6fac2014-10-13 23:42:13 -0600360 return ret;
361}
362
363static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
364{
365 struct tegra_spi_platdata *plat = bus->platdata;
366 struct tegra114_spi_priv *priv = dev_get_priv(bus);
367
368 if (speed > plat->frequency)
369 speed = plat->frequency;
370 priv->freq = speed;
371 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
372
Allen Martin77c42e82013-03-16 18:58:13 +0000373 return 0;
374}
Simon Glassfda6fac2014-10-13 23:42:13 -0600375
376static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
377{
378 struct tegra114_spi_priv *priv = dev_get_priv(bus);
379
380 priv->mode = mode;
381 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
382
383 return 0;
384}
385
386static const struct dm_spi_ops tegra114_spi_ops = {
387 .claim_bus = tegra114_spi_claim_bus,
388 .xfer = tegra114_spi_xfer,
389 .set_speed = tegra114_spi_set_speed,
390 .set_mode = tegra114_spi_set_mode,
391 /*
392 * cs_info is not needed, since we require all chip selects to be
393 * in the device tree explicitly
394 */
395};
396
397static const struct udevice_id tegra114_spi_ids[] = {
398 { .compatible = "nvidia,tegra114-spi" },
399 { }
400};
401
402U_BOOT_DRIVER(tegra114_spi) = {
403 .name = "tegra114_spi",
404 .id = UCLASS_SPI,
405 .of_match = tegra114_spi_ids,
406 .ops = &tegra114_spi_ops,
407 .ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
408 .platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
409 .priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
410 .per_child_auto_alloc_size = sizeof(struct spi_slave),
411 .probe = tegra114_spi_probe,
412};