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Joe Hamman9e3ed392007-12-13 06:45:14 -06001/*
Paul Gortmaker2738bc82009-09-20 20:36:06 -04002 * Copyright 2007,2009 Wind River Systems <www.windriver.com>
Joe Hamman9e3ed392007-12-13 06:45:14 -06003 * Copyright 2007 Embedded Specialties, Inc.
4 * Copyright 2004, 2007 Freescale Semiconductor.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * sbc8548 board configuration file
Paul Gortmaker2738bc82009-09-20 20:36:06 -040027 * Please refer to doc/README.sbc8548 for more info.
Joe Hamman9e3ed392007-12-13 06:45:14 -060028 */
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
Paul Gortmaker2738bc82009-09-20 20:36:06 -040032/*
33 * Top level Makefile configuration choices
34 */
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020035#ifdef CONFIG_PCI
Paul Gortmaker2738bc82009-09-20 20:36:06 -040036#define CONFIG_PCI1
37#endif
38
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020039#ifdef CONFIG_66
Paul Gortmaker2738bc82009-09-20 20:36:06 -040040#define CONFIG_SYS_CLK_DIV 1
41#endif
42
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020043#ifdef CONFIG_33
Paul Gortmaker2738bc82009-09-20 20:36:06 -040044#define CONFIG_SYS_CLK_DIV 2
45#endif
46
Wolfgang Denkd24f2d32010-10-04 19:58:00 +020047#ifdef CONFIG_PCIE
Paul Gortmaker2738bc82009-09-20 20:36:06 -040048#define CONFIG_PCIE1
49#endif
50
51/*
52 * High Level Configuration Options
53 */
Joe Hamman9e3ed392007-12-13 06:45:14 -060054#define CONFIG_BOOKE 1 /* BOOKE */
55#define CONFIG_E500 1 /* BOOKE e500 family */
56#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
57#define CONFIG_MPC8548 1 /* MPC8548 specific */
58#define CONFIG_SBC8548 1 /* SBC8548 board specific */
59
Wolfgang Denk2ae18242010-10-06 09:05:45 +020060#ifndef CONFIG_SYS_TEXT_BASE
61#define CONFIG_SYS_TEXT_BASE 0xfffa0000
62#endif
63
Joe Hamman9e3ed392007-12-13 06:45:14 -060064#undef CONFIG_RIO
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -040065
66#ifdef CONFIG_PCI
67#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
68#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
69#endif
70#ifdef CONFIG_PCIE1
71#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
72#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -060073
74#define CONFIG_TSEC_ENET /* tsec ethernet support */
75#define CONFIG_ENV_OVERWRITE
Joe Hamman9e3ed392007-12-13 06:45:14 -060076
Joe Hamman9e3ed392007-12-13 06:45:14 -060077#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
78
Kumar Galae2b159d2008-01-16 09:05:27 -060079#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
Joe Hamman9e3ed392007-12-13 06:45:14 -060080
Paul Gortmaker2738bc82009-09-20 20:36:06 -040081/*
82 * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
83 */
84#ifndef CONFIG_SYS_CLK_DIV
85#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */
86#endif
87#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -060088
89/*
90 * These can be toggled for performance analysis, otherwise use default.
91 */
92#define CONFIG_L2_CACHE /* toggle L2 cache */
93#define CONFIG_BTB /* toggle branch predition */
Joe Hamman9e3ed392007-12-13 06:45:14 -060094
95/*
96 * Only possible on E500 Version 2 or newer cores.
97 */
98#define CONFIG_ENABLE_36BIT_PHYS 1
99
100#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
101
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
103#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
104#define CONFIG_SYS_MEMTEST_END 0x00400000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600105
Timur Tabie46fedf2011-08-04 18:03:41 -0500106#define CONFIG_SYS_CCSRBAR 0xe0000000
107#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Joe Hamman9e3ed392007-12-13 06:45:14 -0600108
Kumar Gala33b90792008-08-26 23:15:28 -0500109/* DDR Setup */
110#define CONFIG_FSL_DDR2
111#undef CONFIG_FSL_DDR_INTERACTIVE
112#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
113#undef CONFIG_DDR_SPD
114#undef CONFIG_DDR_ECC /* only for ECC DDR module */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600115
Kumar Gala33b90792008-08-26 23:15:28 -0500116#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
117#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
118
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
120#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala33b90792008-08-26 23:15:28 -0500121#define CONFIG_VERY_BIG_RAM
122
123#define CONFIG_NUM_DDR_CONTROLLERS 1
124#define CONFIG_DIMM_SLOTS_PER_CTLR 1
125#define CONFIG_CHIP_SELECTS_PER_CTRL 2
126
127/* I2C addresses of SPD EEPROMs */
128#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600129
130/*
131 * Make sure required options are set
132 */
133#ifndef CONFIG_SPD_EEPROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134 #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600135#endif
136
137#undef CONFIG_CLOCKS_IN_MHZ
138
139/*
140 * FLASH on the Local Bus
141 * Two banks, one 8MB the other 64MB, using the CFI driver.
142 * Boot from BR0/OR0 bank at 0xff80_0000
143 * Alternate BR6/OR6 bank at 0xfb80_0000
144 *
145 * BR0:
146 * Base address 0 = 0xff80_0000 = BR0[0:16] = 1111 1111 1000 0000 0
147 * Port Size = 8 bits = BRx[19:20] = 01
148 * Use GPCM = BRx[24:26] = 000
149 * Valid = BRx[31] = 1
150 *
151 * 0 4 8 12 16 20 24 28
152 * 1111 1111 1000 0000 0000 1000 0000 0001 = ff800801 BR0
153 *
154 * BR6:
155 * Base address 6 = 0xfb80_0000 = BR6[0:16] = 1111 1011 1000 0000 0
156 * Port Size = 32 bits = BRx[19:20] = 11
157 * Use GPCM = BRx[24:26] = 000
158 * Valid = BRx[31] = 1
159 *
160 * 0 4 8 12 16 20 24 28
161 * 1111 1011 1000 0000 0001 1000 0000 0001 = fb801801 BR6
162 *
163 * OR0:
164 * Addr Mask = 8M = OR1[0:16] = 1111 1111 1000 0000 0
165 * XAM = OR0[17:18] = 11
166 * CSNT = OR0[20] = 1
167 * ACS = half cycle delay = OR0[21:22] = 11
168 * SCY = 6 = OR0[24:27] = 0110
169 * TRLX = use relaxed timing = OR0[29] = 1
170 * EAD = use external address latch delay = OR0[31] = 1
171 *
172 * 0 4 8 12 16 20 24 28
173 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 OR0
174 *
175 * OR6:
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400176 * Addr Mask = 64M = OR6[0:16] = 1111 1000 0000 0000 0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600177 * XAM = OR6[17:18] = 11
178 * CSNT = OR6[20] = 1
179 * ACS = half cycle delay = OR6[21:22] = 11
180 * SCY = 6 = OR6[24:27] = 0110
181 * TRLX = use relaxed timing = OR6[29] = 1
182 * EAD = use external address latch delay = OR6[31] = 1
183 *
184 * 0 4 8 12 16 20 24 28
Jeremy McNicollccf1ad52008-05-02 16:10:04 -0400185 * 1111 1000 0000 0000 0110 1110 0110 0101 = f8006e65 OR6
Joe Hamman9e3ed392007-12-13 06:45:14 -0600186 */
187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400189#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600191
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_BR0_PRELIM 0xff800801
193#define CONFIG_SYS_BR6_PRELIM 0xfb801801
Joe Hamman9e3ed392007-12-13 06:45:14 -0600194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_OR0_PRELIM 0xff806e65
196#define CONFIG_SYS_OR6_PRELIM 0xf8006e65
Joe Hamman9e3ed392007-12-13 06:45:14 -0600197
Paul Gortmaker9b3ba242009-09-18 19:08:41 -0400198#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, \
199 CONFIG_SYS_ALT_FLASH}
200#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
201#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#undef CONFIG_SYS_FLASH_CHECKSUM
203#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
204#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600205
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200206#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600207
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200208#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_CFI
210#define CONFIG_SYS_FLASH_EMPTY_INFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600211
212/* CS5 = Local bus peripherals controlled by the EPLD */
213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_BR5_PRELIM 0xf8000801
215#define CONFIG_SYS_OR5_PRELIM 0xff006e65
216#define CONFIG_SYS_EPLD_BASE 0xf8000000
217#define CONFIG_SYS_LED_DISP_BASE 0xf8000000
218#define CONFIG_SYS_USER_SWITCHES_BASE 0xf8100000
219#define CONFIG_SYS_BD_REV 0xf8300000
220#define CONFIG_SYS_EEPROM_BASE 0xf8b00000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600221
222/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400223 * SDRAM on the Local Bus (CS3 and CS4)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400226#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600227
228/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400229 * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600231 *
232 * For BR3, need:
233 * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
234 * port-size = 32-bits = BR2[19:20] = 11
235 * no parity checking = BR2[21:22] = 00
236 * SDRAM for MSEL = BR2[24:26] = 011
237 * Valid = BR[31] = 1
238 *
239 * 0 4 8 12 16 20 24 28
240 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
241 *
242 */
243
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_BR3_PRELIM 0xf0001861
Joe Hamman9e3ed392007-12-13 06:45:14 -0600245
246/*
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400247 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
Joe Hamman9e3ed392007-12-13 06:45:14 -0600248 *
249 * For OR3, need:
250 * 64MB mask for AM, OR3[0:7] = 1111 1100
251 * XAM, OR3[17:18] = 11
252 * 10 columns OR3[19-21] = 011
253 * 12 rows OR3[23-25] = 011
254 * EAD set for extra time OR[31] = 0
255 *
256 * 0 4 8 12 16 20 24 28
257 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
258 */
259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
Joe Hamman9e3ed392007-12-13 06:45:14 -0600261
Paul Gortmaker11d5a622009-09-20 20:36:04 -0400262/*
263 * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM.
264 * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000.
265 *
266 * For BR4, need:
267 * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0
268 * port-size = 32-bits = BR2[19:20] = 11
269 * no parity checking = BR2[21:22] = 00
270 * SDRAM for MSEL = BR2[24:26] = 011
271 * Valid = BR[31] = 1
272 *
273 * 0 4 8 12 16 20 24 28
274 * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861
275 *
276 */
277
278#define CONFIG_SYS_BR4_PRELIM 0xf4001861
279
280/*
281 * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
282 *
283 * For OR4, need:
284 * 64MB mask for AM, OR3[0:7] = 1111 1100
285 * XAM, OR3[17:18] = 11
286 * 10 columns OR3[19-21] = 011
287 * 12 rows OR3[23-25] = 011
288 * EAD set for extra time OR[31] = 0
289 *
290 * 0 4 8 12 16 20 24 28
291 * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0
292 */
293
294#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0
295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */
297#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
298#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
299#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600300
301/*
Joe Hamman9e3ed392007-12-13 06:45:14 -0600302 * Common settings for all Local Bus SDRAM commands.
303 * At run time, either BSMA1516 (for CPU 1.1)
304 * or BSMA1617 (for CPU 1.0) (old)
305 * is OR'ed in too.
306 */
Kumar Galab0fe93ed2009-03-26 01:34:38 -0500307#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
308 | LSDMR_PRETOACT7 \
309 | LSDMR_ACTTORW7 \
310 | LSDMR_BL8 \
311 | LSDMR_WRC4 \
312 | LSDMR_CL3 \
313 | LSDMR_RFEN \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600314 )
315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_INIT_RAM_LOCK 1
317#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200318#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600321
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200322#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Joe Hamman9e3ed392007-12-13 06:45:14 -0600324
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400325/*
326 * For soldered on flash, (128kB/sector) we use 2 sectors for u-boot and
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200327 * one for env+bootpg (CONFIG_SYS_TEXT_BASE=0xfffa_0000, 384kB total). For SODIMM
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400328 * flash (512kB/sector) we use 1 sector for u-boot, and one for env+bootpg
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200329 * (CONFIG_SYS_TEXT_BASE=0xfff0_0000, 1MB total). This dynamically sets the right
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400330 * thing for MONITOR_LEN in both cases.
331 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200332#define CONFIG_SYS_MONITOR_LEN (~CONFIG_SYS_TEXT_BASE + 1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600334
335/* Serial Port */
336#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_NS16550
338#define CONFIG_SYS_NS16550_SERIAL
339#define CONFIG_SYS_NS16550_REG_SIZE 1
Paul Gortmaker2738bc82009-09-20 20:36:06 -0400340#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600343 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
344
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
346#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Joe Hamman9e3ed392007-12-13 06:45:14 -0600347
348/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_HUSH_PARSER
350#ifdef CONFIG_SYS_HUSH_PARSER
351#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Joe Hamman9e3ed392007-12-13 06:45:14 -0600352#endif
353
354/* pass open firmware flat tree */
355#define CONFIG_OF_LIBFDT 1
356#define CONFIG_OF_BOARD_SETUP 1
357#define CONFIG_OF_STDOUT_VIA_ALIAS 1
358
359/*
360 * I2C
361 */
362#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
363#define CONFIG_HARD_I2C /* I2C with hardware support*/
364#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
366#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
367#define CONFIG_SYS_I2C_SLAVE 0x7F
368#define CONFIG_SYS_I2C_OFFSET 0x3000
Joe Hamman9e3ed392007-12-13 06:45:14 -0600369
370/*
371 * General PCI
372 * Memory space is mapped 1-1, but I/O space must start from 0.
373 */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400374#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600376
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400377#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
378#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
379#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400381#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
382#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
383#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
384#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600385
386#ifdef CONFIG_PCIE1
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400387#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
388#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
389#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200390#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400391#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000
392#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
393#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000
394#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600395#endif
396
397#ifdef CONFIG_RIO
398/*
399 * RapidIO MMU
400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000
402#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600403#endif
404
Joe Hamman9e3ed392007-12-13 06:45:14 -0600405#if defined(CONFIG_PCI)
406
Joe Hamman9e3ed392007-12-13 06:45:14 -0600407#define CONFIG_PCI_PNP /* do pci plug-and-play */
408
409#undef CONFIG_EEPRO100
410#undef CONFIG_TULIP
411
Paul Gortmakerfdc7eb92009-09-20 20:36:05 -0400412#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600413
Joe Hamman9e3ed392007-12-13 06:45:14 -0600414#endif /* CONFIG_PCI */
415
416
417#if defined(CONFIG_TSEC_ENET)
418
Joe Hamman9e3ed392007-12-13 06:45:14 -0600419#define CONFIG_MII 1 /* MII PHY management */
420#define CONFIG_TSEC1 1
421#define CONFIG_TSEC1_NAME "eTSEC0"
422#define CONFIG_TSEC2 1
423#define CONFIG_TSEC2_NAME "eTSEC1"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600424#undef CONFIG_MPC85XX_FEC
425
Paul Gortmaker58da8892008-12-11 15:47:50 -0500426#define TSEC1_PHY_ADDR 0x19
427#define TSEC2_PHY_ADDR 0x1a
Joe Hamman9e3ed392007-12-13 06:45:14 -0600428
429#define TSEC1_PHYIDX 0
430#define TSEC2_PHYIDX 0
Paul Gortmakerbd931052008-12-11 15:47:49 -0500431
Joe Hamman9e3ed392007-12-13 06:45:14 -0600432#define TSEC1_FLAGS TSEC_GIGABIT
433#define TSEC2_FLAGS TSEC_GIGABIT
Joe Hamman9e3ed392007-12-13 06:45:14 -0600434
435/* Options are: eTSEC[0-3] */
436#define CONFIG_ETHPRIME "eTSEC0"
437#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
438#endif /* CONFIG_TSEC_ENET */
439
440/*
441 * Environment
442 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200443#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200444#define CONFIG_ENV_SIZE 0x2000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200445#if CONFIG_SYS_TEXT_BASE == 0xfff00000 /* Boot from 64MB SODIMM */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400446#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x80000)
447#define CONFIG_ENV_SECT_SIZE 0x80000 /* 512K(one sector) for env */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200448#elif CONFIG_SYS_TEXT_BASE == 0xfffa0000 /* Boot from 8MB soldered flash */
Paul Gortmakerdd9ca982009-09-25 11:14:11 -0400449#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
450#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
451#else
452#warning undefined environment size/location.
453#endif
Joe Hamman9e3ed392007-12-13 06:45:14 -0600454
455#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600457
458/*
459 * BOOTP options
460 */
461#define CONFIG_BOOTP_BOOTFILESIZE
462#define CONFIG_BOOTP_BOOTPATH
463#define CONFIG_BOOTP_GATEWAY
464#define CONFIG_BOOTP_HOSTNAME
465
466
467/*
468 * Command line configuration.
469 */
470#include <config_cmd_default.h>
471
472#define CONFIG_CMD_PING
473#define CONFIG_CMD_I2C
474#define CONFIG_CMD_MII
475#define CONFIG_CMD_ELF
Becky Bruce199e2622010-06-17 11:37:25 -0500476#define CONFIG_CMD_REGINFO
Joe Hamman9e3ed392007-12-13 06:45:14 -0600477
478#if defined(CONFIG_PCI)
479 #define CONFIG_CMD_PCI
480#endif
481
482
483#undef CONFIG_WATCHDOG /* watchdog disabled */
484
485/*
486 * Miscellaneous configurable options
487 */
Paul Gortmakerad22f922008-12-11 15:47:51 -0500488#define CONFIG_CMDLINE_EDITING /* undef to save memory */
Kim Phillips5be58f52010-07-14 19:47:18 -0500489#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_LONGHELP /* undef to save memory */
491#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
492#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600493#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200494#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600495#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600497#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
499#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
500#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
501#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Joe Hamman9e3ed392007-12-13 06:45:14 -0600502
503/*
504 * For booting Linux, the board info and command line data
505 * have to be in the first 8 MB of memory, since this is
506 * the maximum mapped by the Linux kernel during initialization.
507 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200508#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
Joe Hamman9e3ed392007-12-13 06:45:14 -0600509
Joe Hamman9e3ed392007-12-13 06:45:14 -0600510#if defined(CONFIG_CMD_KGDB)
511#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
512#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
513#endif
514
515/*
516 * Environment Configuration
517 */
518
519/* The mac addresses for all ethernet interface */
520#if defined(CONFIG_TSEC_ENET)
521#define CONFIG_HAS_ETH0
522#define CONFIG_ETHADDR 02:E0:0C:00:00:FD
523#define CONFIG_HAS_ETH1
524#define CONFIG_ETH1ADDR 02:E0:0C:00:01:FD
Joe Hamman9e3ed392007-12-13 06:45:14 -0600525#endif
526
527#define CONFIG_IPADDR 192.168.0.55
528
529#define CONFIG_HOSTNAME sbc8548
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000530#define CONFIG_ROOTPATH "/opt/eldk/ppc_85xx"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000531#define CONFIG_BOOTFILE "/uImage"
Joe Hamman9e3ed392007-12-13 06:45:14 -0600532#define CONFIG_UBOOTPATH /u-boot.bin /* TFTP server */
533
534#define CONFIG_SERVERIP 192.168.0.2
535#define CONFIG_GATEWAYIP 192.168.0.1
536#define CONFIG_NETMASK 255.255.255.0
537
538#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
539
540#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
541#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
542
543#define CONFIG_BAUDRATE 115200
544
545#define CONFIG_EXTRA_ENV_SETTINGS \
546 "netdev=eth0\0" \
547 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
548 "tftpflash=tftpboot $loadaddr $uboot; " \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200549 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
550 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
551 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
552 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
553 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Joe Hamman9e3ed392007-12-13 06:45:14 -0600554 "consoledev=ttyS0\0" \
555 "ramdiskaddr=2000000\0" \
556 "ramdiskfile=uRamdisk\0" \
557 "fdtaddr=c00000\0" \
558 "fdtfile=sbc8548.dtb\0"
559
560#define CONFIG_NFSBOOTCOMMAND \
561 "setenv bootargs root=/dev/nfs rw " \
562 "nfsroot=$serverip:$rootpath " \
563 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
564 "console=$consoledev,$baudrate $othbootargs;" \
565 "tftp $loadaddr $bootfile;" \
566 "tftp $fdtaddr $fdtfile;" \
567 "bootm $loadaddr - $fdtaddr"
568
569
570#define CONFIG_RAMBOOTCOMMAND \
571 "setenv bootargs root=/dev/ram rw " \
572 "console=$consoledev,$baudrate $othbootargs;" \
573 "tftp $ramdiskaddr $ramdiskfile;" \
574 "tftp $loadaddr $bootfile;" \
575 "tftp $fdtaddr $fdtfile;" \
576 "bootm $loadaddr $ramdiskaddr $fdtaddr"
577
578#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
579
580#endif /* __CONFIG_H */