blob: bcfb0348404d33c83782c8d10b6e9cdb39528312 [file] [log] [blame]
Li Yang14aa71e2011-07-26 09:50:46 -05001/*
2 * Copyright 2010-2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/*
24 * QorIQ RDB boards configuration file
25 */
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29#ifdef CONFIG_36BIT
30#define CONFIG_PHYS_64BIT
31#endif
32
33#if defined(CONFIG_P1020MBG)
34#define CONFIG_BOARDNAME "P1020MBG"
35#define CONFIG_P1020
36#define CONFIG_VSC7385_ENET
37#define CONFIG_SLIC
38#define __SW_BOOT_MASK 0x03
39#define __SW_BOOT_NOR 0xe4
40#define __SW_BOOT_SD 0x54
41#endif
42
43#if defined(CONFIG_P1020UTM)
44#define CONFIG_BOARDNAME "P1020UTM"
45#define CONFIG_P1020
46#define __SW_BOOT_MASK 0x03
47#define __SW_BOOT_NOR 0xe0
48#define __SW_BOOT_SD 0x50
49#endif
50
51#if defined(CONFIG_P1020RDB)
52#define CONFIG_BOARDNAME "P1020RDB"
53#define CONFIG_NAND_FSL_ELBC
54#define CONFIG_P1020
55#define CONFIG_SPI_FLASH
56#define CONFIG_VSC7385_ENET
57#define CONFIG_SLIC
58#define __SW_BOOT_MASK 0x03
59#define __SW_BOOT_NOR 0x5c
60#define __SW_BOOT_SPI 0x1c
61#define __SW_BOOT_SD 0x9c
62#define __SW_BOOT_NAND 0xec
63#define __SW_BOOT_PCIE 0x6c
64#endif
65
66#if defined(CONFIG_P1021RDB)
67#define CONFIG_BOARDNAME "P1021RDB"
68#define CONFIG_NAND_FSL_ELBC
69#define CONFIG_P1021
70#define CONFIG_QE
71#define CONFIG_SPI_FLASH
72#define CONFIG_VSC7385_ENET
73#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
74 addresses in the LBC */
75#define __SW_BOOT_MASK 0x03
76#define __SW_BOOT_NOR 0x5c
77#define __SW_BOOT_SPI 0x1c
78#define __SW_BOOT_SD 0x9c
79#define __SW_BOOT_NAND 0xec
80#define __SW_BOOT_PCIE 0x6c
81#endif
82
83#if defined(CONFIG_P1024RDB)
84#define CONFIG_BOARDNAME "P1024RDB"
85#define CONFIG_NAND_FSL_ELBC
86#define CONFIG_P1024
87#define CONFIG_SLIC
88#define CONFIG_SPI_FLASH
89#define __SW_BOOT_MASK 0xf3
90#define __SW_BOOT_NOR 0x00
91#define __SW_BOOT_SPI 0x08
92#define __SW_BOOT_SD 0x04
93#define __SW_BOOT_NAND 0x0c
94#endif
95
96#if defined(CONFIG_P1025RDB)
97#define CONFIG_BOARDNAME "P1025RDB"
98#define CONFIG_NAND_FSL_ELBC
99#define CONFIG_P1025
100#define CONFIG_QE
101#define CONFIG_SLIC
102#define CONFIG_SPI_FLASH
103
104#define CONFIG_SYS_LBC_LBCR 0x00080000 /* Implement conversion of
105 addresses in the LBC */
106#define __SW_BOOT_MASK 0xf3
107#define __SW_BOOT_NOR 0x00
108#define __SW_BOOT_SPI 0x08
109#define __SW_BOOT_SD 0x04
110#define __SW_BOOT_NAND 0x0c
111#endif
112
113#if defined(CONFIG_P2020RDB)
114#define CONFIG_BOARDNAME "P2020RDB"
115#define CONFIG_NAND_FSL_ELBC
116#define CONFIG_P2020
117#define CONFIG_SPI_FLASH
118#define CONFIG_VSC7385_ENET
119#define __SW_BOOT_MASK 0x03
120#define __SW_BOOT_NOR 0xc8
121#define __SW_BOOT_SPI 0x28
122#define __SW_BOOT_SD 0x68 /* or 0x18 */
123#define __SW_BOOT_NAND 0xe8
124#define __SW_BOOT_PCIE 0xa8
125#endif
126
127#ifdef CONFIG_SDCARD
128#define CONFIG_RAMBOOT_SDCARD
129#define CONFIG_SYS_RAMBOOT
130#define CONFIG_SYS_EXTRA_ENV_RELOC
131#define CONFIG_SYS_TEXT_BASE 0x11000000
132#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
133#endif
134
135#ifdef CONFIG_SPIFLASH
136#define CONFIG_RAMBOOT_SPIFLASH
137#define CONFIG_SYS_RAMBOOT
138#define CONFIG_SYS_EXTRA_ENV_RELOC
139#define CONFIG_SYS_TEXT_BASE 0x11000000
140#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
141#endif
142
143#if defined(CONFIG_NAND) && defined(CONFIG_NAND_FSL_ELBC)
144#define CONFIG_NAND_U_BOOT
145#define CONFIG_SYS_EXTRA_ENV_RELOC
146#define CONFIG_SYS_RAMBOOT
147#define CONFIG_SYS_TEXT_BASE_SPL 0xff800000
148#ifdef CONFIG_NAND_SPL
149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL
150#else
151#define CONFIG_SYS_TEXT_BASE 0x11001000
152#endif /* CONFIG_NAND_SPL */
153#endif
154
155#ifndef CONFIG_SYS_TEXT_BASE
156#define CONFIG_SYS_TEXT_BASE 0xeff80000
157#endif
158
159#ifndef CONFIG_RESET_VECTOR_ADDRESS
160#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
161#endif
162
163#ifndef CONFIG_SYS_MONITOR_BASE
164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
165#endif
166
167/* High Level Configuration Options */
168#define CONFIG_BOOKE
169#define CONFIG_E500
170#define CONFIG_MPC85xx
171
172#define CONFIG_MP
173
174#define CONFIG_FSL_ELBC
175#define CONFIG_PCI
176#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
177#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
178#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
179#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
180#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
181
182#define CONFIG_FSL_LAW
183#define CONFIG_TSEC_ENET /* tsec ethernet support */
184#define CONFIG_ENV_OVERWRITE
185
186#define CONFIG_CMD_SATA
187#define CONFIG_SATA_SIL3114
188#define CONFIG_SYS_SATA_MAX_DEVICE 2
189#define CONFIG_LIBATA
190#define CONFIG_LBA48
191
192#if defined(CONFIG_P2020RDB)
193#define CONFIG_SYS_CLK_FREQ 100000000
194#else
195#define CONFIG_SYS_CLK_FREQ 66666666
196#endif
197#define CONFIG_DDR_CLK_FREQ 66666666
198
199#define CONFIG_HWCONFIG
200/*
201 * These can be toggled for performance analysis, otherwise use default.
202 */
203#define CONFIG_L2_CACHE
204#define CONFIG_BTB
205
206#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
Timur Tabibabb3482011-09-06 09:36:06 -0500207
Li Yang14aa71e2011-07-26 09:50:46 -0500208#define CONFIG_ENABLE_36BIT_PHYS
Li Yang14aa71e2011-07-26 09:50:46 -0500209
210#ifdef CONFIG_PHYS_64BIT
211#define CONFIG_ADDR_MAP 1
212#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
213#endif
214
215#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
216#define CONFIG_SYS_MEMTEST_END 0x1fffffff
217#define CONFIG_PANIC_HANG /* do not reset board on panic */
218
219#define CONFIG_SYS_CCSRBAR 0xffe00000
220#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
221
222/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
223 SPL code*/
224#if defined(CONFIG_NAND_U_BOOT) && defined(CONFIG_NAND_SPL)
225#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
226#endif
227
228/* DDR Setup */
229#define CONFIG_FSL_DDR3
230#define CONFIG_DDR_RAW_TIMING
231#define CONFIG_DDR_SPD
232#define CONFIG_SYS_SPD_BUS_NUM 1
233#define SPD_EEPROM_ADDRESS 0x52
York Sun6f5e1dc2011-09-16 13:21:35 -0700234#undef CONFIG_FSL_DDR_INTERACTIVE
Li Yang14aa71e2011-07-26 09:50:46 -0500235
236#ifdef CONFIG_P1020MBG
237#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
238#define CONFIG_CHIP_SELECTS_PER_CTRL 2
239#else
240#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_1G
241#define CONFIG_CHIP_SELECTS_PER_CTRL 1
242#endif
243#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
244#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
245#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
246
247#define CONFIG_NUM_DDR_CONTROLLERS 1
248#define CONFIG_DIMM_SLOTS_PER_CTLR 1
249
250/* Default settings for DDR3 */
251#ifdef CONFIG_P2020RDB
252#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
253#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
254#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
255#define CONFIG_SYS_DDR_CS1_BNDS 0x00000000
256#define CONFIG_SYS_DDR_CS1_CONFIG 0x00000000
257#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
258
259#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
260#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
261#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
262#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
263
264#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
265#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8645F607
266#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
267#define CONFIG_SYS_DDR_RCW_1 0x00000000
268#define CONFIG_SYS_DDR_RCW_2 0x00000000
269#define CONFIG_SYS_DDR_CONTROL 0xC7000000 /* Type = DDR3 */
270#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
271#define CONFIG_SYS_DDR_TIMING_4 0x00220001
272#define CONFIG_SYS_DDR_TIMING_5 0x02401400
273
274#define CONFIG_SYS_DDR_TIMING_3 0x00020000
275#define CONFIG_SYS_DDR_TIMING_0 0x00330104
276#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4644
277#define CONFIG_SYS_DDR_TIMING_2 0x0FA88CCF
278#define CONFIG_SYS_DDR_CLK_CTRL 0x02000000
279#define CONFIG_SYS_DDR_MODE_1 0x00421422
280#define CONFIG_SYS_DDR_MODE_2 0x04000000
281#define CONFIG_SYS_DDR_INTERVAL 0x0C300100
282
283#else
284#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
285#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
286#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
287#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
288#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
289#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
290
291#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
292#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
293#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
294#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
295
296#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
297#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
298#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
299#define CONFIG_SYS_DDR_RCW_1 0x00000000
300#define CONFIG_SYS_DDR_RCW_2 0x00000000
301#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
302#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
303#define CONFIG_SYS_DDR_TIMING_4 0x00220001
304#define CONFIG_SYS_DDR_TIMING_5 0x03402400
305
306#define CONFIG_SYS_DDR_TIMING_3 0x00020000
307#define CONFIG_SYS_DDR_TIMING_0 0x00330004
308#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
309#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
310#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
311#define CONFIG_SYS_DDR_MODE_1 0x40461520
312#define CONFIG_SYS_DDR_MODE_2 0x8000c000
313#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
314#endif
315
316#undef CONFIG_CLOCKS_IN_MHZ
317
318/*
319 * Memory map
320 *
321 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
322 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable(PCIe * 3)
323 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
324 *
325 * Localbus cacheable (TBD)
326 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
327 *
328 * Localbus non-cacheable
329 * 0xec00_0000 0xefff_ffff FLASH Up to 64M non-cacheable
330 * 0xff80_0000 0xff8f_ffff NAND flash 1M non-cacheable
331 * 0xff90_0000 0xff97_ffff L2 SDRAM(REV.) 512K cacheable(optional)
332 * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable
333 * 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable
334 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
335 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
336 */
337
338
339/*
340 * Local Bus Definitions
341 */
342#if defined(CONFIG_P1020MBG)
343#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
344#define CONFIG_SYS_FLASH_BASE 0xec000000
345#elif defined(CONFIG_P1020UTM)
346#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */
347#define CONFIG_SYS_FLASH_BASE 0xee000000
348#else
349#define CONFIG_SYS_MAX_FLASH_SECT 128 /* 16M */
350#define CONFIG_SYS_FLASH_BASE 0xef000000
351#endif
352
353
354#ifdef CONFIG_PHYS_64BIT
355#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
356#else
357#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
358#endif
359
360#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
361 | BR_PS_16 | BR_V)
362
363#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
364
365#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
366#define CONFIG_SYS_FLASH_QUIET_TEST
367#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
368
369#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
370
371#undef CONFIG_SYS_FLASH_CHECKSUM
372#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
373#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
374
375#define CONFIG_FLASH_CFI_DRIVER
376#define CONFIG_SYS_FLASH_CFI
377#define CONFIG_SYS_FLASH_EMPTY_INFO
378#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
379
380/* Nand Flash */
381#ifdef CONFIG_NAND_FSL_ELBC
382#define CONFIG_SYS_NAND_BASE 0xff800000
383#ifdef CONFIG_PHYS_64BIT
384#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
385#else
386#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
387#endif
388
389#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
390#define CONFIG_SYS_MAX_NAND_DEVICE 1
391#define CONFIG_MTD_NAND_VERIFY_WRITE
392#define CONFIG_CMD_NAND
393#define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
394
395/* NAND boot: 4K NAND loader config */
396#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
397#define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) + CONFIG_SYS_NAND_SPL_SIZE)
398#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000 - CONFIG_SYS_NAND_SPL_SIZE)
399#define CONFIG_SYS_NAND_U_BOOT_START 0x11000000
400#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
401#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
402#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
403
404#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS)) \
405 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
406 | BR_PS_8 /* Port Size = 8 bit */ \
407 | BR_MS_FCM /* MSEL = FCM */ \
408 | BR_V) /* valid */
409#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* small page */ \
410 | OR_FCM_CSCT \
411 | OR_FCM_CST \
412 | OR_FCM_CHT \
413 | OR_FCM_SCY_1 \
414 | OR_FCM_TRLX \
415 | OR_FCM_EHTR)
416#endif /* CONFIG_NAND_FSL_ELBC */
417
418#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
419
420#define CONFIG_SYS_INIT_RAM_LOCK
421#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
422#ifdef CONFIG_PHYS_64BIT
423#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
424#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
425/* The assembler doesn't like typecast */
426#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
427 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
428 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
429#else
430/* Initial L1 address */
431#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
432#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
433#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
434#endif
435/* Size of used area in RAM */
436#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
437
438#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
439 GENERATED_GBL_DATA_SIZE)
440#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
441
442#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
443#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
444
445#define CONFIG_SYS_CPLD_BASE 0xffa00000
446#ifdef CONFIG_PHYS_64BIT
447#define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull
448#else
449#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
450#endif
451/* CPLD config size: 1Mb */
452#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
453 BR_PS_8 | BR_V)
454#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
455
456#define CONFIG_SYS_PMC_BASE 0xff980000
457#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
458#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
459 BR_PS_8 | BR_V)
460#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
461 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
462 OR_GPCM_EAD)
463
464#ifdef CONFIG_NAND_U_BOOT
465#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
466#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
467#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
468#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
469#else
470#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
471#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
472#ifdef CONFIG_NAND_FSL_ELBC
473#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
474#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
475#endif
476#endif
477#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
478#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
479
480
481/* Vsc7385 switch */
482#ifdef CONFIG_VSC7385_ENET
483#define CONFIG_SYS_VSC7385_BASE 0xffb00000
484
485#ifdef CONFIG_PHYS_64BIT
486#define CONFIG_SYS_VSC7385_BASE_PHYS 0xfffb00000ull
487#else
488#define CONFIG_SYS_VSC7385_BASE_PHYS CONFIG_SYS_VSC7385_BASE
489#endif
490
491#define CONFIG_SYS_VSC7385_BR_PRELIM \
492 (BR_PHYS_ADDR(CONFIG_SYS_VSC7385_BASE_PHYS) | BR_PS_8 | BR_V)
493#define CONFIG_SYS_VSC7385_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | \
494 OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
495 OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
496
497#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
498#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
499
500/* The size of the VSC7385 firmware image */
501#define CONFIG_VSC7385_IMAGE_SIZE 8192
502#endif
503
504/* Serial Port - controlled on board with jumper J8
505 * open - index 2
506 * shorted - index 1
507 */
508#define CONFIG_CONS_INDEX 1
509#undef CONFIG_SERIAL_SOFTWARE_FIFO
510#define CONFIG_SYS_NS16550
511#define CONFIG_SYS_NS16550_SERIAL
512#define CONFIG_SYS_NS16550_REG_SIZE 1
513#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
514#ifdef CONFIG_NAND_SPL
515#define CONFIG_NS16550_MIN_FUNCTIONS
516#endif
517
518#define CONFIG_SYS_BAUDRATE_TABLE \
519 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
520
521#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
522#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
523
524/* Use the HUSH parser */
525#define CONFIG_SYS_HUSH_PARSER
526#ifdef CONFIG_SYS_HUSH_PARSER
527#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
528#endif
529
530/*
531 * Pass open firmware flat tree
532 */
533#define CONFIG_OF_LIBFDT
534#define CONFIG_OF_BOARD_SETUP
535#define CONFIG_OF_STDOUT_VIA_ALIAS
536
537#define CONFIG_SYS_64BIT_VSPRINTF
538#define CONFIG_SYS_64BIT_STRTOUL
539
540/* new uImage format support */
541#define CONFIG_FIT
542#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
543
544/* I2C */
545#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
546#define CONFIG_HARD_I2C /* I2C with hardware support */
547#undef CONFIG_SOFT_I2C /* I2C bit-banged */
548#define CONFIG_I2C_MULTI_BUS
549#define CONFIG_I2C_CMD_TREE
550#define CONFIG_SYS_I2C_SPEED 400000 /* I2C spd and slave address */
551#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
552#define CONFIG_SYS_I2C_SLAVE 0x7F
553#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe this addr */
554#define CONFIG_SYS_I2C_OFFSET 0x3000
555#define CONFIG_SYS_I2C2_OFFSET 0x3100
556#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
557
558/*
559 * I2C2 EEPROM
560 */
561#undef CONFIG_ID_EEPROM
562
563#define CONFIG_RTC_PT7C4338
564#define CONFIG_SYS_I2C_RTC_ADDR 0x68
565#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
566
567/* enable read and write access to EEPROM */
568#define CONFIG_CMD_EEPROM
569#define CONFIG_SYS_I2C_MULTI_EEPROMS
570#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
571#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
572#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
573
574/*
575 * eSPI - Enhanced SPI
576 */
577#define CONFIG_HARD_SPI
578#define CONFIG_FSL_ESPI
579
580#if defined(CONFIG_SPI_FLASH)
581#define CONFIG_SPI_FLASH_SPANSION
582#define CONFIG_CMD_SF
583#define CONFIG_SF_DEFAULT_SPEED 10000000
584#define CONFIG_SF_DEFAULT_MODE 0
585#endif
586
587#if defined(CONFIG_PCI)
588/*
589 * General PCI
590 * Memory space is mapped 1-1, but I/O space must start from 0.
591 */
592
593/* controller 2, direct to uli, tgtid 2, Base address 9000 */
594#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT"
595#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
596#ifdef CONFIG_PHYS_64BIT
597#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
598#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
599#else
600#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
601#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
602#endif
603#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
604#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
605#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
606#ifdef CONFIG_PHYS_64BIT
607#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
608#else
609#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
610#endif
611#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
612
613/* controller 1, Slot 2, tgtid 1, Base address a000 */
614#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT"
615#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
616#ifdef CONFIG_PHYS_64BIT
617#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
618#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
619#else
620#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
621#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
622#endif
623#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
624#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
625#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
626#ifdef CONFIG_PHYS_64BIT
627#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull
628#else
629#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
630#endif
631#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
632
Li Yang14aa71e2011-07-26 09:50:46 -0500633#define CONFIG_NET_MULTI
634#define CONFIG_PCI_PNP /* do pci plug-and-play */
635#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
636#define CONFIG_CMD_PCI
637#define CONFIG_CMD_NET
638
639#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
640#define CONFIG_DOS_PARTITION
641#endif /* CONFIG_PCI */
642
643#if defined(CONFIG_TSEC_ENET)
644
645#ifndef CONFIG_NET_MULTI
646#define CONFIG_NET_MULTI
647#endif
648
649#define CONFIG_MII /* MII PHY management */
650#define CONFIG_TSEC1
651#define CONFIG_TSEC1_NAME "eTSEC1"
652#define CONFIG_TSEC2
653#define CONFIG_TSEC2_NAME "eTSEC2"
654#define CONFIG_TSEC3
655#define CONFIG_TSEC3_NAME "eTSEC3"
656
657#define TSEC1_PHY_ADDR 2
658#define TSEC2_PHY_ADDR 0
659#define TSEC3_PHY_ADDR 1
660
661#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
662#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
663#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
664
665#define TSEC1_PHYIDX 0
666#define TSEC2_PHYIDX 0
667#define TSEC3_PHYIDX 0
668
669#define CONFIG_ETHPRIME "eTSEC1"
670
671#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
672
673#define CONFIG_HAS_ETH0
674#define CONFIG_HAS_ETH1
675#define CONFIG_HAS_ETH2
676#endif /* CONFIG_TSEC_ENET */
677
678#ifdef CONFIG_QE
679/* QE microcode/firmware address */
680#define CONFIG_SYS_QE_FW_ADDR 0xefec0000
681#define CONFIG_SYS_QE_FW_LENGTH 0x10000
682#endif /* CONFIG_QE */
683
684#ifdef CONFIG_P1025RDB
685/*
686 * QE UEC ethernet configuration
687 */
688#define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120)
689
690#undef CONFIG_UEC_ETH
691#define CONFIG_PHY_MODE_NEED_CHANGE
692
693#define CONFIG_UEC_ETH1 /* ETH1 */
694#define CONFIG_HAS_ETH0
695
696#ifdef CONFIG_UEC_ETH1
697#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
698#define CONFIG_SYS_UEC1_RX_CLK QE_CLK12 /* CLK12 for MII */
699#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9 /* CLK9 for MII */
700#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
701#define CONFIG_SYS_UEC1_PHY_ADDR 0x0 /* 0x0 for MII */
702#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
703#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
704#endif /* CONFIG_UEC_ETH1 */
705
706#define CONFIG_UEC_ETH5 /* ETH5 */
707#define CONFIG_HAS_ETH1
708
709#ifdef CONFIG_UEC_ETH5
710#define CONFIG_SYS_UEC5_UCC_NUM 4 /* UCC5 */
711#define CONFIG_SYS_UEC5_RX_CLK QE_CLK_NONE
712#define CONFIG_SYS_UEC5_TX_CLK QE_CLK13 /* CLK 13 for RMII */
713#define CONFIG_SYS_UEC5_ETH_TYPE FAST_ETH
714#define CONFIG_SYS_UEC5_PHY_ADDR 0x3 /* 0x3 for RMII */
715#define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
716#define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
717#endif /* CONFIG_UEC_ETH5 */
718#endif /* CONFIG_P1025RDB */
719
720/*
721 * Environment
722 */
723#ifdef CONFIG_SYS_RAMBOOT
724#ifdef CONFIG_RAMBOOT_SPIFLASH
725#define CONFIG_ENV_IS_IN_SPI_FLASH
726#define CONFIG_ENV_SPI_BUS 0
727#define CONFIG_ENV_SPI_CS 0
728#define CONFIG_ENV_SPI_MAX_HZ 10000000
729#define CONFIG_ENV_SPI_MODE 0
730#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
731#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
732#define CONFIG_ENV_SECT_SIZE 0x10000
733#elif defined(CONFIG_RAMBOOT_SDCARD)
734#define CONFIG_ENV_IS_IN_MMC
735#define CONFIG_ENV_SIZE 0x2000
736#define CONFIG_SYS_MMC_ENV_DEV 0
737#elif defined(CONFIG_NAND_U_BOOT)
738#define CONFIG_ENV_IS_IN_NAND
739#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
740#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
741#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
742#else
743#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
744#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
745#define CONFIG_ENV_SIZE 0x2000
746#endif
747#else
748#define CONFIG_ENV_IS_IN_FLASH
749#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
750#define CONFIG_ENV_ADDR 0xfff80000
751#else
752#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
753#endif
754#define CONFIG_ENV_SIZE 0x2000
755#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
756#endif
757
758#define CONFIG_LOADS_ECHO /* echo on for serial download */
759#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
760
761/*
762 * Command line configuration.
763 */
764#include <config_cmd_default.h>
765
766#define CONFIG_CMD_IRQ
767#define CONFIG_CMD_PING
768#define CONFIG_CMD_I2C
769#define CONFIG_CMD_MII
770#define CONFIG_CMD_DATE
771#define CONFIG_CMD_ELF
772#define CONFIG_CMD_SETEXPR
773#define CONFIG_CMD_REGINFO
774
775/*
776 * USB
777 */
778#define CONFIG_HAS_FSL_DR_USB
779
780#if defined(CONFIG_HAS_FSL_DR_USB)
781#define CONFIG_USB_EHCI
782
783#ifdef CONFIG_USB_EHCI
784#define CONFIG_CMD_USB
785#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
786#define CONFIG_USB_EHCI_FSL
787#define CONFIG_USB_STORAGE
788#endif
789#endif
790
791#define CONFIG_MMC
792
793#ifdef CONFIG_MMC
794#define CONFIG_FSL_ESDHC
795#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
796#define CONFIG_CMD_MMC
797#define CONFIG_GENERIC_MMC
798#endif
799
800#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \
801 || defined(CONFIG_FSL_SATA)
802#define CONFIG_CMD_EXT2
803#define CONFIG_CMD_FAT
804#define CONFIG_DOS_PARTITION
805#endif
806
807#undef CONFIG_WATCHDOG /* watchdog disabled */
808
809/*
810 * Miscellaneous configurable options
811 */
812#define CONFIG_SYS_LONGHELP /* undef to save memory */
813#define CONFIG_CMDLINE_EDITING /* Command-line editing */
814#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
815#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
816#if defined(CONFIG_CMD_KGDB)
817#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
818#else
819#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
820#endif
821#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
822 /* Print Buffer Size */
823#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
824#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
825#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
826
827/*
828 * For booting Linux, the board info and command line data
829 * have to be in the first 64 MB of memory, since this is
830 * the maximum mapped by the Linux kernel during initialization.
831 */
832#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
833#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
834
835#if defined(CONFIG_CMD_KGDB)
836#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
837#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
838#endif
839
840/*
841 * Environment Configuration
842 */
843#define CONFIG_HOSTNAME unknown
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000844#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000845#define CONFIG_BOOTFILE "uImage"
Li Yang14aa71e2011-07-26 09:50:46 -0500846#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
847
848/* default location for tftp and bootm */
849#define CONFIG_LOADADDR 1000000
850
851#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
852#define CONFIG_BOOTARGS /* the boot command will set bootargs */
853
854#define CONFIG_BAUDRATE 115200
855
856#ifdef __SW_BOOT_NOR
857#define __NOR_RST_CMD \
858norboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NOR 1; \
859i2c mw 18 3 __SW_BOOT_MASK 1; reset
860#endif
861#ifdef __SW_BOOT_SPI
862#define __SPI_RST_CMD \
863spiboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SPI 1; \
864i2c mw 18 3 __SW_BOOT_MASK 1; reset
865#endif
866#ifdef __SW_BOOT_SD
867#define __SD_RST_CMD \
868sdboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_SD 1; \
869i2c mw 18 3 __SW_BOOT_MASK 1; reset
870#endif
871#ifdef __SW_BOOT_NAND
872#define __NAND_RST_CMD \
873nandboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_NAND 1; \
874i2c mw 18 3 __SW_BOOT_MASK 1; reset
875#endif
876#ifdef __SW_BOOT_PCIE
877#define __PCIE_RST_CMD \
878pciboot=i2c dev 1; i2c mw 18 1 __SW_BOOT_PCIE 1; \
879i2c mw 18 3 __SW_BOOT_MASK 1; reset
880#endif
881
882#define CONFIG_EXTRA_ENV_SETTINGS \
883"netdev=eth0\0" \
884"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
885"loadaddr=1000000\0" \
886"bootfile=uImage\0" \
887"tftpflash=tftpboot $loadaddr $uboot; " \
888 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
889 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
890 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
891 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
892 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
893"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
894"consoledev=ttyS0\0" \
895"ramdiskaddr=2000000\0" \
896"ramdiskfile=rootfs.ext2.gz.uboot\0" \
897"fdtaddr=c00000\0" \
898"bdev=sda1\0" \
899"jffs2nor=mtdblock3\0" \
900"norbootaddr=ef080000\0" \
901"norfdtaddr=ef040000\0" \
902"jffs2nand=mtdblock9\0" \
903"nandbootaddr=100000\0" \
904"nandfdtaddr=80000\0" \
905"ramdisk_size=120000\0" \
906"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
907"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
908MK_STR(__NOR_RST_CMD)"\0" \
909MK_STR(__SPI_RST_CMD)"\0" \
910MK_STR(__SD_RST_CMD)"\0" \
911MK_STR(__NAND_RST_CMD)"\0" \
912MK_STR(__PCIE_RST_CMD)"\0"
913
914#define CONFIG_NFSBOOTCOMMAND \
915"setenv bootargs root=/dev/nfs rw " \
916"nfsroot=$serverip:$rootpath " \
917"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
918"console=$consoledev,$baudrate $othbootargs;" \
919"tftp $loadaddr $bootfile;" \
920"tftp $fdtaddr $fdtfile;" \
921"bootm $loadaddr - $fdtaddr"
922
923#define CONFIG_HDBOOT \
924"setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
925"console=$consoledev,$baudrate $othbootargs;" \
926"usb start;" \
927"ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
928"ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
929"bootm $loadaddr - $fdtaddr"
930
931#define CONFIG_USB_FAT_BOOT \
932"setenv bootargs root=/dev/ram rw " \
933"console=$consoledev,$baudrate $othbootargs " \
934"ramdisk_size=$ramdisk_size;" \
935"usb start;" \
936"fatload usb 0:2 $loadaddr $bootfile;" \
937"fatload usb 0:2 $fdtaddr $fdtfile;" \
938"fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
939"bootm $loadaddr $ramdiskaddr $fdtaddr"
940
941#define CONFIG_USB_EXT2_BOOT \
942"setenv bootargs root=/dev/ram rw " \
943"console=$consoledev,$baudrate $othbootargs " \
944"ramdisk_size=$ramdisk_size;" \
945"usb start;" \
946"ext2load usb 0:4 $loadaddr $bootfile;" \
947"ext2load usb 0:4 $fdtaddr $fdtfile;" \
948"ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
949"bootm $loadaddr $ramdiskaddr $fdtaddr"
950
951#define CONFIG_NORBOOT \
952"setenv bootargs root=/dev/$jffs2nor rw " \
953"console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
954"bootm $norbootaddr - $norfdtaddr"
955
956#define CONFIG_RAMBOOTCOMMAND \
957"setenv bootargs root=/dev/ram rw " \
958"console=$consoledev,$baudrate $othbootargs " \
959"ramdisk_size=$ramdisk_size;" \
960"tftp $ramdiskaddr $ramdiskfile;" \
961"tftp $loadaddr $bootfile;" \
962"tftp $fdtaddr $fdtfile;" \
963"bootm $loadaddr $ramdiskaddr $fdtaddr"
964
965#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
966
967#endif /* __CONFIG_H */