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gerrit.cesnet.cz / github / trini / u-boot / b3a2bbe1a4ed3db48c0d54c5ca5c8024c36dc070 / . / arch / powerpc / cpu / mpc85xx / p3041_serdes.c
blob: c88c78c4e66a5482cca6b1301e54874753e479bb [file] [log] [blame]
Kumar Galad5d2cd42010-07-04 13:07:08 -0500[diff] [blame]1/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]4 * SPDX-License-Identifier: GPL-2.0+
Kumar Galad5d2cd42010-07-04 13:07:08 -0500[diff] [blame]5 */
6
7#include <common.h>
8#include <asm/fsl_serdes.h>
9#include <asm/processor.h>
10#include <asm/io.h>
11#include "fsl_corenet_serdes.h"
12
13static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
14 [0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
15 PCIE4, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
16 SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
17 [0x4] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
18 PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
19 SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, },
20 [0xb] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
21 PCIE2, AURORA, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
22 SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
23 [0x10] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1,
24 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
25 NONE, NONE, SATA1, SATA2, },
26 [0x11] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
27 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
28 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
29 [0x13] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
30 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
31 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
32 XAUI_FM1, XAUI_FM1, },
33 [0x14] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
34 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
35 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
36 SGMII_FM1_DTSEC4, },
37 [0x15] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
38 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
39 NONE, NONE, SATA1, SATA2, },
40 [0x16] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2,
41 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
42 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SRIO1, SRIO1, SRIO1,
43 SRIO1, },
44 [0x17] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
45 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
46 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
47 [0x18] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
48 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
49 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
50 NONE, NONE, },
51 [0x1b] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
52 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
53 NONE, NONE, SATA1, SATA2, },
54 [0x1d] = {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1,
55 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3, NONE, NONE,
56 SATA1, SATA2, },
57 [0x20] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
58 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
59 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
60 XAUI_FM1, XAUI_FM1, },
61 [0x21] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
62 AURORA, AURORA, PCIE3, PCIE3, PCIE3, PCIE3,
63 SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3,
64 SGMII_FM1_DTSEC4, },
65 [0x22] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1,
66 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
67 NONE, NONE, SATA1, SATA2, },
68 [0x23] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
69 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
70 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
71 [0x24] = {PCIE1, PCIE1, PCIE1, PCIE1, SRIO2, SRIO2, SRIO1, SRIO1,
72 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
73 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
74 NONE, NONE, },
75 [0x28] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
76 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
77 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, NONE, NONE, SATA1, SATA2, },
78 [0x29] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
79 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
80 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
81 NONE, NONE, },
82 [0x2a] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
83 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
84 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, XAUI_FM1, XAUI_FM1,
85 XAUI_FM1, XAUI_FM1, },
86 [0x2b] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2, PCIE2, PCIE2,
87 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
88 NONE, NONE, SATA1, SATA2, },
89 [0x2f] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO2, SRIO2, SRIO1, SRIO1,
90 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
91 NONE, NONE, SATA1, SATA2, },
92 [0x31] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
93 AURORA, AURORA, SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
94 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, SGMII_FM1_DTSEC5, NONE,
95 NONE, NONE, },
96 [0x33] = {PCIE1, PCIE1, PCIE3, PCIE3, SRIO1, SRIO1, SRIO1, SRIO1,
97 AURORA, AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1,
98 NONE, NONE, SATA1, SATA2, },
99 [0x34] = {PCIE1, PCIE1, PCIE1, PCIE1, SGMII_FM1_DTSEC1,
100 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
101 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
102 NONE, SATA1, SATA2, },
103 [0x35] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2,
104 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
105 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
106 [0x36] = {PCIE1, PCIE1, PCIE3, PCIE3, SGMII_FM1_DTSEC1,
107 SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA,
108 AURORA, XAUI_FM1, XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE,
109 NONE, SATA1, SATA2, },
110 [0x37] = {PCIE1, PCIE1, PCIE3, PCIE3, PCIE2, PCIE2,
111 SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4, AURORA, AURORA, XAUI_FM1,
112 XAUI_FM1, XAUI_FM1, XAUI_FM1, NONE, NONE, SATA1, SATA2, },
113};
114
115enum srds_prtcl serdes_get_prtcl(int cfg, int lane)
116{
117 if (!serdes_lane_enabled(lane))
118 return NONE;
119
120 return serdes_cfg_tbl[cfg][lane];
121}
122
123int is_serdes_prtcl_valid(u32 prtcl) {
124 int i;
125
Axel Line51e47d2013-05-26 15:00:30 +0800[diff] [blame]126 if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
Kumar Galad5d2cd42010-07-04 13:07:08 -0500[diff] [blame]127 return 0;
128
129 for (i = 0; i < SRDS_MAX_LANES; i++) {
130 if (serdes_cfg_tbl[prtcl][i] != NONE)
131 return 1;
132 }
133
134 return 0;
135}