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wdenkb4676a22003-12-07 19:24:00 +00001/*
2 * GNU General Public License for more details.
3 *
4 * MATRIX Vision GmbH / June 2002-Nov 2003
5 * Andre Schwarz
6 */
7
8#include <common.h>
9#include <mpc824x.h>
10#include <asm/io.h>
11#include <ns16550.h>
12
13#ifdef CONFIG_PCI
wdenkd4ca31c2004-01-02 14:00:00 +000014#include <pci.h>
wdenkb4676a22003-12-07 19:24:00 +000015#endif
16
wdenkd4ca31c2004-01-02 14:00:00 +000017u32 get_BoardType (void);
wdenkb4676a22003-12-07 19:24:00 +000018
19#define PCI_CONFIG(b,d,f,r) cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
wdenkd4ca31c2004-01-02 14:00:00 +000020 | ((d&0x1f)<<11) \
21 | ((f&0x7)<<7) \
22 | (r&0xfc) )
wdenkb4676a22003-12-07 19:24:00 +000023
wdenkd4ca31c2004-01-02 14:00:00 +000024int mv_pci_read (int bus, int dev, int func, int reg)
wdenkb4676a22003-12-07 19:24:00 +000025{
wdenkd4ca31c2004-01-02 14:00:00 +000026 *(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
27 asm ("sync");
28 return cpu_to_le32 (*(u32 *) (0xfee00cfc));
wdenkb4676a22003-12-07 19:24:00 +000029}
30
wdenkd4ca31c2004-01-02 14:00:00 +000031u32 get_BoardType ()
wdenkb4676a22003-12-07 19:24:00 +000032{
wdenkd4ca31c2004-01-02 14:00:00 +000033 return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
34}
35
36void init_2nd_DUART (void)
37{
38 NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
wdenkb4676a22003-12-07 19:24:00 +000039 int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
wdenkd4ca31c2004-01-02 14:00:00 +000040
41 *(u8 *) (0xfc004511) = 0x1;
42 NS16550_init (console, clock_divisor);
wdenkb4676a22003-12-07 19:24:00 +000043}
wdenkd4ca31c2004-01-02 14:00:00 +000044void hw_watchdog_reset (void)
wdenkb4676a22003-12-07 19:24:00 +000045{
wdenkd4ca31c2004-01-02 14:00:00 +000046 if (get_BoardType () == 0) {
47 *(u32 *) (0xff000005) = 0;
48 asm ("sync");
wdenkb4676a22003-12-07 19:24:00 +000049 }
50}
51int checkboard (void)
52{
53 DECLARE_GLOBAL_DATA_PTR;
wdenkd4ca31c2004-01-02 14:00:00 +000054 ulong busfreq = get_bus_freq (0);
55 char buf[32];
56 u32 BoardType = get_BoardType ();
wdenkb4676a22003-12-07 19:24:00 +000057 char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
58 char *p;
59 bd_t *bd = gd->bd;
60
wdenkd4ca31c2004-01-02 14:00:00 +000061 hw_watchdog_reset ();
wdenkb4676a22003-12-07 19:24:00 +000062
wdenkd4ca31c2004-01-02 14:00:00 +000063 printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
64 printf (" Found %s running at %s MHz memory clock.\n",
65 BoardName[BoardType], strmhz (buf, busfreq));
wdenkb4676a22003-12-07 19:24:00 +000066
wdenkd4ca31c2004-01-02 14:00:00 +000067 init_2nd_DUART ();
wdenkb4676a22003-12-07 19:24:00 +000068
wdenkd4ca31c2004-01-02 14:00:00 +000069 if ((p = getenv ("console_nr")) != NULL) {
70 unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
71
72 bd->bi_baudrate &= ~3;
73 bd->bi_baudrate |= con_nr & 3;
wdenkb4676a22003-12-07 19:24:00 +000074 }
75 return 0;
76}
77
78long int initdram (int board_type)
79{
wdenkd4ca31c2004-01-02 14:00:00 +000080 int i, cnt;
81 volatile uchar *base = CFG_SDRAM_BASE;
82 volatile ulong *addr;
83 ulong save[32];
84 ulong val, ret = 0;
wdenkb4676a22003-12-07 19:24:00 +000085
wdenkd4ca31c2004-01-02 14:00:00 +000086 for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
87 cnt >>= 1) {
88 addr = (volatile ulong *) base + cnt;
wdenkb4676a22003-12-07 19:24:00 +000089 save[i++] = *addr;
90 *addr = ~cnt;
91 }
92
wdenkd4ca31c2004-01-02 14:00:00 +000093 addr = (volatile ulong *) base;
wdenkb4676a22003-12-07 19:24:00 +000094 save[i] = *addr;
95 *addr = 0;
96
97 if (*addr != 0) {
98 *addr = save[i];
99 goto Done;
100 }
101
wdenkd4ca31c2004-01-02 14:00:00 +0000102 for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
103 addr = (volatile ulong *) base + cnt;
wdenkb4676a22003-12-07 19:24:00 +0000104 val = *addr;
105 *addr = save[--i];
106 if (val != ~cnt) {
wdenkd4ca31c2004-01-02 14:00:00 +0000107 ulong new_bank0_end = cnt * sizeof (long) - 1;
108 ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
109 ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
110
111 mear1 = (mear1 & 0xFFFFFF00) |
112 ((new_bank0_end & MICR_ADDR_MASK) >>
113 MICR_ADDR_SHIFT);
wdenkb4676a22003-12-07 19:24:00 +0000114 emear1 = (emear1 & 0xFFFFFF00) |
wdenkd4ca31c2004-01-02 14:00:00 +0000115 ((new_bank0_end & MICR_ADDR_MASK) >>
116 MICR_EADDR_SHIFT);
117 mpc824x_mpc107_setreg (MEAR1, mear1);
118 mpc824x_mpc107_setreg (EMEAR1, emear1);
119 ret = cnt * sizeof (long);
wdenkb4676a22003-12-07 19:24:00 +0000120 goto Done;
121 }
122 }
123
124 ret = CFG_MAX_RAM_SIZE;
wdenkd4ca31c2004-01-02 14:00:00 +0000125 Done:
wdenkb4676a22003-12-07 19:24:00 +0000126 return ret;
127}
128
129/* ------------------------------------------------------------------------- */
wdenkd4ca31c2004-01-02 14:00:00 +0000130u8 *dhcp_vendorex_prep (u8 * e)
wdenkb4676a22003-12-07 19:24:00 +0000131{
wdenkd4ca31c2004-01-02 14:00:00 +0000132 char *ptr;
wdenkb4676a22003-12-07 19:24:00 +0000133
134 /* DHCP vendor-class-identifier = 60 */
wdenkd4ca31c2004-01-02 14:00:00 +0000135 if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
136 *e++ = 60;
137 *e++ = strlen (ptr);
138 while (*ptr)
139 *e++ = *ptr++;
140 }
wdenkb4676a22003-12-07 19:24:00 +0000141 /* my DHCP_CLIENT_IDENTIFIER = 61 */
wdenkd4ca31c2004-01-02 14:00:00 +0000142 if ((ptr = getenv ("dhcp_client_id"))) {
143 *e++ = 61;
144 *e++ = strlen (ptr);
145 while (*ptr)
146 *e++ = *ptr++;
147 }
148 return e;
wdenkb4676a22003-12-07 19:24:00 +0000149}
wdenkd4ca31c2004-01-02 14:00:00 +0000150
151u8 *dhcp_vendorex_proc (u8 * popt)
wdenkb4676a22003-12-07 19:24:00 +0000152{
wdenkd4ca31c2004-01-02 14:00:00 +0000153 return NULL;
wdenkb4676a22003-12-07 19:24:00 +0000154}
wdenkd4ca31c2004-01-02 14:00:00 +0000155
wdenkb4676a22003-12-07 19:24:00 +0000156/* ------------------------------------------------------------------------- */
157
158/*
159 * Initialize PCI Devices
160 */
161#ifdef CONFIG_PCI
wdenkd4ca31c2004-01-02 14:00:00 +0000162void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
wdenkb4676a22003-12-07 19:24:00 +0000163{
164 u32 cnt;
wdenkd4ca31c2004-01-02 14:00:00 +0000165
166 printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
167 PCI_FUNC (dev));
168 for (cnt = 0; cnt < 6; cnt++)
169 pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
170 0x0);
171 printf ("done\n");
wdenkb4676a22003-12-07 19:24:00 +0000172}
173
wdenkd4ca31c2004-01-02 14:00:00 +0000174void duart_setup (u32 base, u16 divisor)
wdenkb4676a22003-12-07 19:24:00 +0000175{
wdenkd4ca31c2004-01-02 14:00:00 +0000176 printf ("duart setup ...");
177 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
178 out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
179 out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
180 out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
181 out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
182 out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
183 printf ("done\n");
wdenkb4676a22003-12-07 19:24:00 +0000184}
185
wdenkd4ca31c2004-01-02 14:00:00 +0000186void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
187 pci_dev_t bridge, unsigned char irq)
wdenkb4676a22003-12-07 19:24:00 +0000188{
189 pci_dev_t d;
wdenkd4ca31c2004-01-02 14:00:00 +0000190 unsigned char bus;
191 unsigned short vendor, class;
wdenkb4676a22003-12-07 19:24:00 +0000192
wdenkd4ca31c2004-01-02 14:00:00 +0000193 pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
194 for (d = PCI_BDF (bus, 0, 0);
195 d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
196 PCI_MAX_PCI_FUNCTIONS - 1);
197 d += PCI_BDF (0, 0, 1)) {
198 pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
199 if (vendor != 0xffff && vendor != 0x0000) {
200 pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
201 &class);
202 if (class == PCI_CLASS_BRIDGE_PCI)
203 pci_mvblue_fixup_irq_behind_bridge (hose, d,
204 irq);
wdenkb4676a22003-12-07 19:24:00 +0000205 else
wdenkd4ca31c2004-01-02 14:00:00 +0000206 pci_hose_write_config_byte (hose, d,
207 PCI_INTERRUPT_LINE,
208 irq);
wdenkb4676a22003-12-07 19:24:00 +0000209 }
210 }
211}
212
213#define MV_MAX_PCI_BUSSES 3
214#define SLOT0_IRQ 3
215#define SLOT1_IRQ 4
wdenkd4ca31c2004-01-02 14:00:00 +0000216void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
wdenkb4676a22003-12-07 19:24:00 +0000217{
wdenkd4ca31c2004-01-02 14:00:00 +0000218 unsigned char line = 0xff;
219 unsigned short class;
wdenkb4676a22003-12-07 19:24:00 +0000220
wdenkd4ca31c2004-01-02 14:00:00 +0000221 if (PCI_BUS (dev) == 0) {
222 switch (PCI_DEV (dev)) {
223 case 0xd:
224 if (get_BoardType () == 0) {
wdenkb4676a22003-12-07 19:24:00 +0000225 line = 1;
226 } else
227 /* mvBL */
wdenkd4ca31c2004-01-02 14:00:00 +0000228 line = 2;
229 break;
230 case 0xe:
wdenkb4676a22003-12-07 19:24:00 +0000231 /* mvBB: IDE */
232 line = 2;
wdenkd4ca31c2004-01-02 14:00:00 +0000233 pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
wdenkb4676a22003-12-07 19:24:00 +0000234 break;
235 case 0xf:
236 /* mvBB: Slot0 (Grabber) */
wdenkd4ca31c2004-01-02 14:00:00 +0000237 pci_hose_read_config_word (hose, dev,
238 PCI_CLASS_DEVICE, &class);
239 if (class == PCI_CLASS_BRIDGE_PCI) {
240 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
241 SLOT0_IRQ);
wdenkb4676a22003-12-07 19:24:00 +0000242 line = 0xff;
243 } else
244 line = SLOT0_IRQ;
245 break;
246 case 0x10:
247 /* mvBB: Slot1 */
wdenkd4ca31c2004-01-02 14:00:00 +0000248 pci_hose_read_config_word (hose, dev,
249 PCI_CLASS_DEVICE, &class);
250 if (class == PCI_CLASS_BRIDGE_PCI) {
251 pci_mvblue_fixup_irq_behind_bridge (hose, dev,
252 SLOT1_IRQ);
wdenkb4676a22003-12-07 19:24:00 +0000253 line = 0xff;
254 } else
255 line = SLOT1_IRQ;
256 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000257 default:
258 printf ("***pci_scan: illegal dev = 0x%08x\n",
259 PCI_DEV (dev));
wdenkb4676a22003-12-07 19:24:00 +0000260 line = 0xff;
261 break;
wdenkd4ca31c2004-01-02 14:00:00 +0000262 }
263 pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
264 line);
wdenkb4676a22003-12-07 19:24:00 +0000265 }
266}
267
268struct pci_controller hose = {
wdenkd4ca31c2004-01-02 14:00:00 +0000269 fixup_irq:pci_mvblue_fixup_irq
wdenkb4676a22003-12-07 19:24:00 +0000270};
271
wdenkd4ca31c2004-01-02 14:00:00 +0000272void pci_init_board (void)
wdenkb4676a22003-12-07 19:24:00 +0000273{
wdenkd4ca31c2004-01-02 14:00:00 +0000274 pci_mpc824x_init (&hose);
wdenkb4676a22003-12-07 19:24:00 +0000275}
276#endif