wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Functions to access the TSC2000 controller on TRAB board (used for scanning |
| 3 | * thermo sensors) |
| 4 | * |
| 5 | * Copyright (C) 2003 Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de |
| 6 | * |
| 7 | * Copyright (C) 2002 DENX Software Engineering, Wolfgang Denk, wd@denx.de |
| 8 | * |
| 9 | * See file CREDITS for list of people who contributed to this |
| 10 | * project. |
| 11 | * |
| 12 | * This program is free software; you can redistribute it and/or |
| 13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of |
| 15 | * the License, or (at your option) any later version. |
| 16 | * |
| 17 | * This program is distributed in the hope that it will be useful, |
| 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 20 | * GNU General Public License for more details. |
| 21 | * |
| 22 | * You should have received a copy of the GNU General Public License |
| 23 | * along with this program; if not, write to the Free Software |
| 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 25 | * MA 02111-1307 USA |
| 26 | */ |
| 27 | |
| 28 | #ifndef _TSC2000_H_ |
| 29 | #define _TSC2000_H_ |
| 30 | |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 31 | /* temperature channel multiplexer definitions */ |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 32 | #define CON_MUX0 (gpio->pccon = (gpio->pccon & 0x0FFFFFCFF) | 0x00000100) |
| 33 | #define CLR_MUX0 (gpio->pcdat &= 0x0FFEF) |
| 34 | #define SET_MUX0 (gpio->pcdat |= 0x00010) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 35 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 36 | #define CON_MUX1 (gpio->pccon = (gpio->pccon & 0x0FFFFF3FF) | 0x00000400) |
| 37 | #define CLR_MUX1 (gpio->pcdat &= 0x0FFDF) |
| 38 | #define SET_MUX1 (gpio->pcdat |= 0x00020) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 39 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 40 | #define CON_MUX1_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFFCFFF) | 0x00001000) |
| 41 | #define CLR_MUX1_ENABLE (gpio->pcdat |= 0x00040) |
| 42 | #define SET_MUX1_ENABLE (gpio->pcdat &= 0x0FFBF) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 43 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 44 | #define CON_MUX2_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFF3FFF) | 0x00004000) |
| 45 | #define CLR_MUX2_ENABLE (gpio->pcdat |= 0x00080) |
| 46 | #define SET_MUX2_ENABLE (gpio->pcdat &= 0x0FF7F) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 47 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 48 | #define CON_MUX3_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFFCFFFF) | 0x00010000) |
| 49 | #define CLR_MUX3_ENABLE (gpio->pcdat |= 0x00100) |
| 50 | #define SET_MUX3_ENABLE (gpio->pcdat &= 0x0FEFF) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 51 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 52 | #define CON_MUX4_ENABLE (gpio->pccon = (gpio->pccon & 0x0FFF3FFFF) | 0x00040000) |
| 53 | #define CLR_MUX4_ENABLE (gpio->pcdat |= 0x00200) |
| 54 | #define SET_MUX4_ENABLE (gpio->pcdat &= 0x0FDFF) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 55 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 56 | #define CON_SEL_TEMP_V_0 (gpio->pccon = (gpio->pccon & 0x0FFCFFFFF) | \ |
| 57 | 0x00100000) |
| 58 | #define CLR_SEL_TEMP_V_0 (gpio->pcdat &= 0x0FBFF) |
| 59 | #define SET_SEL_TEMP_V_0 (gpio->pcdat |= 0x00400) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 60 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 61 | #define CON_SEL_TEMP_V_1 (gpio->pccon = (gpio->pccon & 0x0FF3FFFFF) | \ |
| 62 | 0x00400000) |
| 63 | #define CLR_SEL_TEMP_V_1 (gpio->pcdat &= 0x0F7FF) |
| 64 | #define SET_SEL_TEMP_V_1 (gpio->pcdat |= 0x00800) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 65 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 66 | #define CON_SEL_TEMP_V_2 (gpio->pccon = (gpio->pccon & 0x0FCFFFFFF) | \ |
| 67 | 0x01000000) |
| 68 | #define CLR_SEL_TEMP_V_2 (gpio->pcdat &= 0x0EFFF) |
| 69 | #define SET_SEL_TEMP_V_2 (gpio->pcdat |= 0x01000) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 70 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 71 | #define CON_SEL_TEMP_V_3 (gpio->pccon = (gpio->pccon & 0x0F3FFFFFF) | \ |
| 72 | 0x04000000) |
| 73 | #define CLR_SEL_TEMP_V_3 (gpio->pcdat &= 0x0DFFF) |
| 74 | #define SET_SEL_TEMP_V_3 (gpio->pcdat |= 0x02000) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 75 | |
| 76 | /* TSC2000 register definition */ |
| 77 | #define TSC2000_REG_X ((0 << 11) | (0 << 5)) |
| 78 | #define TSC2000_REG_Y ((0 << 11) | (1 << 5)) |
| 79 | #define TSC2000_REG_Z1 ((0 << 11) | (2 << 5)) |
| 80 | #define TSC2000_REG_Z2 ((0 << 11) | (3 << 5)) |
| 81 | #define TSC2000_REG_BAT1 ((0 << 11) | (5 << 5)) |
| 82 | #define TSC2000_REG_BAT2 ((0 << 11) | (6 << 5)) |
| 83 | #define TSC2000_REG_AUX1 ((0 << 11) | (7 << 5)) |
| 84 | #define TSC2000_REG_AUX2 ((0 << 11) | (8 << 5)) |
| 85 | #define TSC2000_REG_TEMP1 ((0 << 11) | (9 << 5)) |
| 86 | #define TSC2000_REG_TEMP2 ((0 << 11) | (0xA << 5)) |
| 87 | #define TSC2000_REG_DAC ((0 << 11) | (0xB << 5)) |
| 88 | #define TSC2000_REG_ZERO ((0 << 11) | (0x10 << 5)) |
| 89 | #define TSC2000_REG_ADC ((1 << 11) | (0 << 5)) |
| 90 | #define TSC2000_REG_DACCTL ((1 << 11) | (2 << 5)) |
| 91 | #define TSC2000_REG_REF ((1 << 11) | (3 << 5)) |
| 92 | #define TSC2000_REG_RESET ((1 << 11) | (4 << 5)) |
| 93 | #define TSC2000_REG_CONFIG ((1 << 11) | (5 << 5)) |
| 94 | |
| 95 | /* bit definition of TSC2000 ADC register */ |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 96 | #define TC_PSM (1 << 15) |
| 97 | #define TC_STS (1 << 14) |
| 98 | #define TC_AD3 (1 << 13) |
| 99 | #define TC_AD2 (1 << 12) |
| 100 | #define TC_AD1 (1 << 11) |
| 101 | #define TC_AD0 (1 << 10) |
| 102 | #define TC_RS1 (1 << 9) |
| 103 | #define TC_RS0 (1 << 8) |
| 104 | #define TC_AV1 (1 << 7) |
| 105 | #define TC_AV0 (1 << 6) |
| 106 | #define TC_CL1 (1 << 5) |
| 107 | #define TC_CL0 (1 << 4) |
| 108 | #define TC_PV2 (1 << 3) |
| 109 | #define TC_PV1 (1 << 2) |
| 110 | #define TC_PV0 (1 << 1) |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 111 | |
| 112 | /* default value for TSC2000 ADC register for use with touch functions */ |
| 113 | #define DEFAULT_ADC (TC_PV1 | TC_AV0 | TC_AV1 | TC_RS0) |
| 114 | |
| 115 | #define TSC2000_DELAY_BASE 500 |
| 116 | #define TSC2000_NO_SENSOR -0x10000 |
| 117 | |
Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 118 | #define ERROR_BATTERY 220 /* must be adjusted, if R68 is changed on TRAB */ |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 119 | |
wdenk | f5300ab | 2003-09-12 15:35:15 +0000 | [diff] [blame] | 120 | void tsc2000_write(unsigned short, unsigned short); |
| 121 | unsigned short tsc2000_read (unsigned short); |
| 122 | u16 tsc2000_read_channel (unsigned int); |
| 123 | void tsc2000_set_mux (unsigned int); |
| 124 | void tsc2000_set_range (unsigned int); |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 125 | void tsc2000_reg_init (void); |
| 126 | s32 tsc2000_contact_temp (void); |
wdenk | f5300ab | 2003-09-12 15:35:15 +0000 | [diff] [blame] | 127 | void spi_wait_transmit_done (void); |
Mike Frysinger | f6e3a1f | 2009-08-13 00:32:14 -0400 | [diff] [blame] | 128 | void tsc2000_spi_init(void); |
wdenk | f5300ab | 2003-09-12 15:35:15 +0000 | [diff] [blame] | 129 | int tsc2000_interpolate(long value, long data[][2], long *result); |
| 130 | void adc_wait_conversion_done(void); |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 131 | |
| 132 | |
| 133 | static inline void SET_CS_TOUCH(void) |
| 134 | { |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 135 | struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 136 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 137 | gpio->pddat &= 0x5FF; |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 138 | } |
| 139 | |
| 140 | |
| 141 | static inline void CLR_CS_TOUCH(void) |
| 142 | { |
kevin.morfitt@fearnside-systems.co.uk | eb0ae7f | 2009-10-10 13:33:11 +0900 | [diff] [blame] | 143 | struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio(); |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 144 | |
C Nauman | d9abba8 | 2010-10-26 23:04:31 +0900 | [diff] [blame] | 145 | gpio->pddat |= 0x200; |
wdenk | 4f7cb08 | 2003-09-11 23:06:34 +0000 | [diff] [blame] | 146 | } |
| 147 | |
| 148 | #endif /* _TSC2000_H_ */ |