blob: 95ff6a70d83e6f984431be9666134ebdb8849a64 [file] [log] [blame]
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +05301/**
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * This file provides support for the board-specific CPLD used on some Freescale
7 * reference boards.
8 *
9 * The following macros need to be defined:
10 *
11 * CONFIG_SYS_CPLD_BASE-The virtual address of the base of the CPLD register map
12 */
13
14#include <common.h>
15#include <command.h>
16#include <asm/io.h>
17
18#include "cpld.h"
19
20u8 cpld_read(unsigned int reg)
21{
22 void *p = (void *)CONFIG_SYS_CPLD_BASE;
23
24 return in_8(p + reg);
25}
26
27void cpld_write(unsigned int reg, u8 value)
28{
29 void *p = (void *)CONFIG_SYS_CPLD_BASE;
30
31 out_8(p + reg, value);
32}
33
34/**
35 * Set the boot bank to the alternate bank
36 */
37void cpld_set_altbank(void)
38{
39 u8 reg = CPLD_READ(flash_ctl_status);
40
41 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
42
43 CPLD_WRITE(flash_ctl_status, reg);
44 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
45}
46
47/**
48 * Set the boot bank to the default bank
49 */
50void cpld_set_defbank(void)
51{
52 u8 reg = CPLD_READ(flash_ctl_status);
53
54 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
55
56 CPLD_WRITE(flash_ctl_status, reg);
57 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
58}
59
60#ifdef DEBUG
61static void cpld_dump_regs(void)
62{
63 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
64 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
65 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
66 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
67 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
68 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
69 printf("int_status = 0x%02x\n", CPLD_READ(int_status));
70 printf("flash_ctl_status = 0x%02x\n", CPLD_READ(flash_ctl_status));
71 printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
York Sun78e56992016-11-21 11:25:26 -080072#if defined(CONFIG_TARGET_T1040D4D4RDB) || defined(CONFIG_TARGET_T1042D4RDB)
Priyanka Jain4b6067a2015-06-05 15:29:02 +053073 printf("int_mask = 0x%02x\n", CPLD_READ(int_mask));
74#else
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +053075 printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
Priyanka Jain4b6067a2015-06-05 15:29:02 +053076#endif
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +053077 printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
78 printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
79 printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
80 printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
81 printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
82 putc('\n');
83}
84#endif
85
86int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
87{
88 int rc = 0;
89
90 if (argc <= 1)
91 return cmd_usage(cmdtp);
92
93 if (strcmp(argv[1], "reset") == 0) {
94 if (strcmp(argv[2], "altbank") == 0)
95 cpld_set_altbank();
96 else
97 cpld_set_defbank();
98#ifdef DEBUG
99 } else if (strcmp(argv[1], "dump") == 0) {
100 cpld_dump_regs();
101#endif
102 } else
103 rc = cmd_usage(cmdtp);
104
105 return rc;
106}
107
108U_BOOT_CMD(
109 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
110 "Reset the board or alternate bank",
111 "reset - hard reset to default bank\n"
112 "cpld reset altbank - reset to alternate bank\n"
113#ifdef DEBUG
114 "cpld dump - display the CPLD registers\n"
115#endif
116 );