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Fabio Estevam7891e252012-09-13 03:18:20 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Fabio Estevam7891e252012-09-13 03:18:20 +00007 */
8
Fabio Estevam7891e252012-09-13 03:18:20 +00009#include <asm/arch/clock.h>
10#include <asm/arch/imx-regs.h>
11#include <asm/arch/iomux.h>
Pierre Aubertc1747972013-06-04 09:00:15 +020012#include <asm/arch/mx6-pins.h>
Fabio Estevam7891e252012-09-13 03:18:20 +000013#include <asm/errno.h>
14#include <asm/gpio.h>
15#include <asm/imx-common/iomux-v3.h>
Otavio Salvador85449db2013-03-16 08:05:07 +000016#include <asm/imx-common/boot_mode.h>
Fabio Estevam7891e252012-09-13 03:18:20 +000017#include <mmc.h>
18#include <fsl_esdhc.h>
19#include <miiphy.h>
20#include <netdev.h>
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -050021#include <asm/arch/mxc_hdmi.h>
22#include <asm/arch/crm_regs.h>
23#include <linux/fb.h>
24#include <ipu_pixfmt.h>
25#include <asm/io.h>
26#include <asm/arch/sys_proto.h>
Fabio Estevam7891e252012-09-13 03:18:20 +000027DECLARE_GLOBAL_DATA_PTR;
28
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000029#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevam7891e252012-09-13 03:18:20 +000032
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000033#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevam7891e252012-09-13 03:18:20 +000036
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000037#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
Fabio Estevam7891e252012-09-13 03:18:20 +000039
Fabio Estevam8bfa9c62013-11-08 16:20:54 -020040#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
41 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
42
Fabio Estevam7891e252012-09-13 03:18:20 +000043int dram_init(void)
44{
45 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
46
47 return 0;
48}
49
Eric Nelson6e142322012-10-03 07:26:38 +000050iomux_v3_cfg_t const uart1_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -070051 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
52 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
Fabio Estevam7891e252012-09-13 03:18:20 +000053};
54
Eric Nelson6e142322012-10-03 07:26:38 +000055iomux_v3_cfg_t const enet_pads[] = {
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000056 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelson10fda482013-11-04 17:00:51 -070058 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000063 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelson10fda482013-11-04 17:00:51 -070065 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000070 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
Fabio Estevama0d21fc2012-09-18 17:24:23 +000071 /* AR8031 PHY Reset */
Eric Nelson10fda482013-11-04 17:00:51 -070072 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
Fabio Estevama0d21fc2012-09-18 17:24:23 +000073};
74
75static void setup_iomux_enet(void)
76{
77 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
78
79 /* Reset AR8031 PHY */
80 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
81 udelay(500);
82 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
83}
84
Shawn Guode7d02a2012-12-30 14:14:59 +000085iomux_v3_cfg_t const usdhc2_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -070086 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
Shawn Guode7d02a2012-12-30 14:14:59 +000097};
98
Eric Nelson6e142322012-10-03 07:26:38 +000099iomux_v3_cfg_t const usdhc3_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700100 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
110 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
Fabio Estevam7891e252012-09-13 03:18:20 +0000111};
112
Shawn Guode7d02a2012-12-30 14:14:59 +0000113iomux_v3_cfg_t const usdhc4_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700114 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
Shawn Guode7d02a2012-12-30 14:14:59 +0000124};
125
Fabio Estevam8bfa9c62013-11-08 16:20:54 -0200126iomux_v3_cfg_t const ecspi1_pads[] = {
127 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
128 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
129 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
130 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
131};
132
133static void setup_spi(void)
134{
135 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
136}
137
Fabio Estevambe4ab3d2013-12-04 01:08:16 -0200138iomux_v3_cfg_t const di0_pads[] = {
139 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
140 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
141 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
142};
143
Fabio Estevam7891e252012-09-13 03:18:20 +0000144static void setup_iomux_uart(void)
145{
146 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
147}
148
149#ifdef CONFIG_FSL_ESDHC
Shawn Guode7d02a2012-12-30 14:14:59 +0000150struct fsl_esdhc_cfg usdhc_cfg[3] = {
151 {USDHC2_BASE_ADDR},
Fabio Estevam7891e252012-09-13 03:18:20 +0000152 {USDHC3_BASE_ADDR},
Shawn Guode7d02a2012-12-30 14:14:59 +0000153 {USDHC4_BASE_ADDR},
Fabio Estevam7891e252012-09-13 03:18:20 +0000154};
155
Shawn Guode7d02a2012-12-30 14:14:59 +0000156#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
157#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
158
Fabio Estevam7891e252012-09-13 03:18:20 +0000159int board_mmc_getcd(struct mmc *mmc)
160{
Shawn Guode7d02a2012-12-30 14:14:59 +0000161 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
Otavio Salvador60bb4622013-03-16 08:05:06 +0000162 int ret = 0;
Shawn Guode7d02a2012-12-30 14:14:59 +0000163
164 switch (cfg->esdhc_base) {
165 case USDHC2_BASE_ADDR:
Otavio Salvador60bb4622013-03-16 08:05:06 +0000166 ret = !gpio_get_value(USDHC2_CD_GPIO);
167 break;
Shawn Guode7d02a2012-12-30 14:14:59 +0000168 case USDHC3_BASE_ADDR:
Otavio Salvador60bb4622013-03-16 08:05:06 +0000169 ret = !gpio_get_value(USDHC3_CD_GPIO);
170 break;
171 case USDHC4_BASE_ADDR:
172 ret = 1; /* eMMC/uSDHC4 is always present */
173 break;
Shawn Guode7d02a2012-12-30 14:14:59 +0000174 }
Otavio Salvador60bb4622013-03-16 08:05:06 +0000175
176 return ret;
Fabio Estevam7891e252012-09-13 03:18:20 +0000177}
178
179int board_mmc_init(bd_t *bis)
180{
Otavio Salvadorf07e2862013-04-19 03:41:58 +0000181 s32 status = 0;
Shawn Guode7d02a2012-12-30 14:14:59 +0000182 int i;
Fabio Estevam7891e252012-09-13 03:18:20 +0000183
Otavio Salvador28ff9172013-03-16 08:05:05 +0000184 /*
185 * According to the board_mmc_init() the following map is done:
186 * (U-boot device node) (Physical Port)
187 * mmc0 SD2
188 * mmc1 SD3
189 * mmc2 eMMC
190 */
Shawn Guode7d02a2012-12-30 14:14:59 +0000191 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
192 switch (i) {
193 case 0:
194 imx_iomux_v3_setup_multiple_pads(
195 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
196 gpio_direction_input(USDHC2_CD_GPIO);
197 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
198 break;
199 case 1:
200 imx_iomux_v3_setup_multiple_pads(
201 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
202 gpio_direction_input(USDHC3_CD_GPIO);
203 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
204 break;
205 case 2:
206 imx_iomux_v3_setup_multiple_pads(
207 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
208 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
209 break;
210 default:
211 printf("Warning: you configured more USDHC controllers"
Otavio Salvadorf07e2862013-04-19 03:41:58 +0000212 "(%d) then supported by the board (%d)\n",
213 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
214 return status;
215 }
Shawn Guode7d02a2012-12-30 14:14:59 +0000216
Otavio Salvadorf07e2862013-04-19 03:41:58 +0000217 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
Shawn Guode7d02a2012-12-30 14:14:59 +0000218 }
219
Otavio Salvadorf07e2862013-04-19 03:41:58 +0000220 return status;
Fabio Estevam7891e252012-09-13 03:18:20 +0000221}
222#endif
223
Fabio Estevama0d21fc2012-09-18 17:24:23 +0000224int mx6_rgmii_rework(struct phy_device *phydev)
225{
226 unsigned short val;
227
228 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
229 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
230 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
231 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
232
233 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
234 val &= 0xffe3;
235 val |= 0x18;
236 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
237
238 /* introduce tx clock delay */
239 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
240 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
241 val |= 0x0100;
242 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
243
244 return 0;
245}
246
247int board_phy_config(struct phy_device *phydev)
248{
249 mx6_rgmii_rework(phydev);
250
251 if (phydev->drv->config)
252 phydev->drv->config(phydev);
253
254 return 0;
255}
256
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500257#if defined(CONFIG_VIDEO_IPUV3)
Fabio Estevamd9b89462013-09-04 15:12:38 -0300258struct display_info_t {
259 int bus;
260 int addr;
261 int pixfmt;
262 int (*detect)(struct display_info_t const *dev);
263 void (*enable)(struct display_info_t const *dev);
264 struct fb_videomode mode;
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500265};
266
Fabio Estevamd9b89462013-09-04 15:12:38 -0300267static int detect_hdmi(struct display_info_t const *dev)
268{
269 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
270 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
271}
272
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200273
274static void disable_lvds(struct display_info_t const *dev)
275{
276 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
277
278 int reg = readl(&iomux->gpr[2]);
279
280 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
281 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
282
283 writel(reg, &iomux->gpr[2]);
284}
285
Fabio Estevamd9b89462013-09-04 15:12:38 -0300286static void do_enable_hdmi(struct display_info_t const *dev)
287{
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200288 disable_lvds(dev);
Fabio Estevamd9b89462013-09-04 15:12:38 -0300289 imx_enable_hdmi_phy();
290}
291
292static void enable_lvds(struct display_info_t const *dev)
293{
294 struct iomuxc *iomux = (struct iomuxc *)
295 IOMUXC_BASE_ADDR;
296 u32 reg = readl(&iomux->gpr[2]);
Fabio Estevam119e9902013-12-04 01:08:17 -0200297 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
298 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
Fabio Estevamd9b89462013-09-04 15:12:38 -0300299 writel(reg, &iomux->gpr[2]);
300}
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200301
Fabio Estevamd9b89462013-09-04 15:12:38 -0300302static struct display_info_t const displays[] = {{
303 .bus = -1,
304 .addr = 0,
Fabio Estevam119e9902013-12-04 01:08:17 -0200305 .pixfmt = IPU_PIX_FMT_RGB666,
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200306 .detect = NULL,
307 .enable = enable_lvds,
Fabio Estevamd9b89462013-09-04 15:12:38 -0300308 .mode = {
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200309 .name = "Hannstar-XGA",
Fabio Estevamd9b89462013-09-04 15:12:38 -0300310 .refresh = 60,
311 .xres = 1024,
312 .yres = 768,
313 .pixclock = 15385,
314 .left_margin = 220,
315 .right_margin = 40,
316 .upper_margin = 21,
317 .lower_margin = 7,
318 .hsync_len = 60,
319 .vsync_len = 10,
320 .sync = FB_SYNC_EXT,
321 .vmode = FB_VMODE_NONINTERLACED
322} }, {
323 .bus = -1,
324 .addr = 0,
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200325 .pixfmt = IPU_PIX_FMT_RGB24,
326 .detect = detect_hdmi,
327 .enable = do_enable_hdmi,
Fabio Estevamd9b89462013-09-04 15:12:38 -0300328 .mode = {
Fabio Estevamb48e3b02013-11-25 10:34:26 -0200329 .name = "HDMI",
Fabio Estevamd9b89462013-09-04 15:12:38 -0300330 .refresh = 60,
331 .xres = 1024,
332 .yres = 768,
333 .pixclock = 15385,
334 .left_margin = 220,
335 .right_margin = 40,
336 .upper_margin = 21,
337 .lower_margin = 7,
338 .hsync_len = 60,
339 .vsync_len = 10,
340 .sync = FB_SYNC_EXT,
341 .vmode = FB_VMODE_NONINTERLACED
342} } };
343
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500344int board_video_skip(void)
345{
Fabio Estevamd9b89462013-09-04 15:12:38 -0300346 int i;
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500347 int ret;
Fabio Estevamd9b89462013-09-04 15:12:38 -0300348 char const *panel = getenv("panel");
349 if (!panel) {
350 for (i = 0; i < ARRAY_SIZE(displays); i++) {
351 struct display_info_t const *dev = displays+i;
Fabio Estevam1601ba42013-09-11 18:14:29 -0300352 if (dev->detect && dev->detect(dev)) {
Fabio Estevamd9b89462013-09-04 15:12:38 -0300353 panel = dev->mode.name;
354 printf("auto-detected panel %s\n", panel);
355 break;
356 }
357 }
358 if (!panel) {
359 panel = displays[0].mode.name;
360 printf("No panel detected: default to %s\n", panel);
Fabio Estevam59f46f42013-09-11 18:14:30 -0300361 i = 0;
Fabio Estevamd9b89462013-09-04 15:12:38 -0300362 }
363 } else {
364 for (i = 0; i < ARRAY_SIZE(displays); i++) {
365 if (!strcmp(panel, displays[i].mode.name))
366 break;
367 }
368 }
369 if (i < ARRAY_SIZE(displays)) {
370 ret = ipuv3_fb_init(&displays[i].mode, 0,
371 displays[i].pixfmt);
372 if (!ret) {
373 displays[i].enable(displays+i);
374 printf("Display: %s (%ux%u)\n",
375 displays[i].mode.name,
376 displays[i].mode.xres,
377 displays[i].mode.yres);
378 } else
379 printf("LCD %s cannot be configured: %d\n",
380 displays[i].mode.name, ret);
381 } else {
382 printf("unsupported panel %s\n", panel);
383 return -EINVAL;
384 }
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500385
Fabio Estevamd9b89462013-09-04 15:12:38 -0300386 return 0;
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500387}
388
389static void setup_display(void)
390{
391 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
Fabio Estevamd9b89462013-09-04 15:12:38 -0300392 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500393 int reg;
394
Fabio Estevambe4ab3d2013-12-04 01:08:16 -0200395 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
396 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
397
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500398 enable_ipu_clock();
399 imx_setup_hdmi();
400
Fabio Estevamd9b89462013-09-04 15:12:38 -0300401 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
Liu Ying12307432013-11-29 22:38:39 +0800402 reg = readl(&mxc_ccm->CCGR3);
Fabio Estevamd9b89462013-09-04 15:12:38 -0300403 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
404 writel(reg, &mxc_ccm->CCGR3);
405
406 /* set LDB0, LDB1 clk select to 011/011 */
407 reg = readl(&mxc_ccm->cs2cdr);
408 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
409 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
410 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
411 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
412 writel(reg, &mxc_ccm->cs2cdr);
413
414 reg = readl(&mxc_ccm->cscmr2);
415 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
416 writel(reg, &mxc_ccm->cscmr2);
417
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500418 reg = readl(&mxc_ccm->chsccdr);
419 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
420 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
Fabio Estevamd9b89462013-09-04 15:12:38 -0300421 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
422 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500423 writel(reg, &mxc_ccm->chsccdr);
Fabio Estevamd9b89462013-09-04 15:12:38 -0300424
425 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
426 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
427 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
428 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
429 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
430 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
431 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
432 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
433 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
434 writel(reg, &iomux->gpr[2]);
435
436 reg = readl(&iomux->gpr[3]);
437 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
438 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
439 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
440 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
441 writel(reg, &iomux->gpr[3]);
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500442}
443#endif /* CONFIG_VIDEO_IPUV3 */
444
445/*
446 * Do not overwrite the console
447 * Use always serial for U-Boot console
448 */
449int overwrite_console(void)
450{
451 return 1;
452}
453
Fabio Estevama0d21fc2012-09-18 17:24:23 +0000454int board_eth_init(bd_t *bis)
455{
456 int ret;
457
458 setup_iomux_enet();
459
460 ret = cpu_eth_init(bis);
461 if (ret)
462 printf("FEC MXC: %s:failed\n", __func__);
463
Fabio Estevamcb427fe2013-09-12 22:03:22 -0300464 return ret;
Fabio Estevama0d21fc2012-09-18 17:24:23 +0000465}
466
Fabio Estevam7891e252012-09-13 03:18:20 +0000467int board_early_init_f(void)
468{
469 setup_iomux_uart();
Pardeep Kumar Singla58cc9782013-07-25 12:12:14 -0500470#if defined(CONFIG_VIDEO_IPUV3)
471 setup_display();
472#endif
Fabio Estevam7891e252012-09-13 03:18:20 +0000473
474 return 0;
475}
476
477int board_init(void)
478{
479 /* address of boot parameters */
480 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
481
Fabio Estevam8bfa9c62013-11-08 16:20:54 -0200482#ifdef CONFIG_MXC_SPI
483 setup_spi();
484#endif
485
Fabio Estevam7891e252012-09-13 03:18:20 +0000486 return 0;
487}
488
Otavio Salvador85449db2013-03-16 08:05:07 +0000489#ifdef CONFIG_CMD_BMODE
490static const struct boot_mode board_boot_modes[] = {
491 /* 4 bit bus width */
492 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
493 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
494 /* 8 bit bus width */
495 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
496 {NULL, 0},
497};
498#endif
499
500int board_late_init(void)
501{
502#ifdef CONFIG_CMD_BMODE
503 add_board_boot_modes(board_boot_modes);
504#endif
505
506 return 0;
507}
508
Fabio Estevam7891e252012-09-13 03:18:20 +0000509int checkboard(void)
510{
Pierre Aubertc1747972013-06-04 09:00:15 +0200511 puts("Board: MX6-SabreSD\n");
Fabio Estevam7891e252012-09-13 03:18:20 +0000512 return 0;
513}