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Fabio Estevam7dd65452012-09-24 08:09:33 +00001/*
2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
3 *
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Fabio Estevam7dd65452012-09-24 08:09:33 +00007 */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/clock.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/iomux.h>
Eric Nelsonb47abc32013-11-13 16:36:19 -070014#include <asm/arch/mx6-pins.h>
Fabio Estevam7dd65452012-09-24 08:09:33 +000015#include <asm/errno.h>
16#include <asm/gpio.h>
17#include <asm/imx-common/iomux-v3.h>
Renato Frias19578162013-05-13 18:01:12 +000018#include <asm/imx-common/mxc_i2c.h>
Otavio Salvador85449db2013-03-16 08:05:07 +000019#include <asm/imx-common/boot_mode.h>
Fabio Estevam7dd65452012-09-24 08:09:33 +000020#include <mmc.h>
21#include <fsl_esdhc.h>
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000022#include <miiphy.h>
23#include <netdev.h>
Fabio Estevamdce67bd2012-10-02 11:20:12 +000024#include <asm/arch/sys_proto.h>
Renato Frias19578162013-05-13 18:01:12 +000025#include <i2c.h>
Fabio Estevamdce67bd2012-10-02 11:20:12 +000026
Fabio Estevam7dd65452012-09-24 08:09:33 +000027DECLARE_GLOBAL_DATA_PTR;
28
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000029#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
30 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
31 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevam7dd65452012-09-24 08:09:33 +000032
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000033#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
34 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
Fabio Estevam7dd65452012-09-24 08:09:33 +000036
Benoît Thébaudeau7e2173c2013-04-26 01:34:47 +000037#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000039
Renato Frias19578162013-05-13 18:01:12 +000040#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
41 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
42 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
43
44#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
45
Fabio Estevam7dd65452012-09-24 08:09:33 +000046int dram_init(void)
47{
48 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
49
50 return 0;
51}
52
Eric Nelson6e142322012-10-03 07:26:38 +000053iomux_v3_cfg_t const uart4_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -070054 MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
55 MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
Fabio Estevam7dd65452012-09-24 08:09:33 +000056};
57
Eric Nelson6e142322012-10-03 07:26:38 +000058iomux_v3_cfg_t const enet_pads[] = {
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000059 MX6_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelson10fda482013-11-04 17:00:51 -070061 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000066 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelson10fda482013-11-04 17:00:51 -070068 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
71 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
72 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
Eric Nelsoncfb8b9d2013-02-19 10:07:01 +000073 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
Fabio Estevamfe5ebe92012-09-25 08:43:57 +000074};
75
Renato Frias19578162013-05-13 18:01:12 +000076/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
77struct i2c_pads_info i2c_pad_info1 = {
78 .scl = {
79 .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
Eric Nelson10fda482013-11-04 17:00:51 -070080 .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
Renato Frias19578162013-05-13 18:01:12 +000081 .gp = IMX_GPIO_NR(2, 30)
82 },
83 .sda = {
84 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
Eric Nelson10fda482013-11-04 17:00:51 -070085 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
Renato Frias19578162013-05-13 18:01:12 +000086 .gp = IMX_GPIO_NR(4, 13)
87 }
88};
89
90/*
91 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
92 * Compass Sensor, Accelerometer, Res Touch
93 */
94struct i2c_pads_info i2c_pad_info2 = {
95 .scl = {
96 .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
Eric Nelson10fda482013-11-04 17:00:51 -070097 .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
Renato Frias19578162013-05-13 18:01:12 +000098 .gp = IMX_GPIO_NR(1, 3)
99 },
100 .sda = {
101 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
Eric Nelson10fda482013-11-04 17:00:51 -0700102 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
Renato Frias19578162013-05-13 18:01:12 +0000103 .gp = IMX_GPIO_NR(3, 18)
104 }
105};
106
107iomux_v3_cfg_t const i2c3_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700108 MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL),
Renato Frias19578162013-05-13 18:01:12 +0000109};
110
Renato Friasa1f67802013-05-13 18:01:13 +0000111iomux_v3_cfg_t const port_exp[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700112 MX6_PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
Renato Friasa1f67802013-05-13 18:01:13 +0000113};
114
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000115static void setup_iomux_enet(void)
116{
117 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
118}
119
Eric Nelson6e142322012-10-03 07:26:38 +0000120iomux_v3_cfg_t const usdhc3_pads[] = {
Eric Nelson10fda482013-11-04 17:00:51 -0700121 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
127 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
129 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
130 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 MX6_PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
Fabio Estevam7dd65452012-09-24 08:09:33 +0000133};
134
135static void setup_iomux_uart(void)
136{
137 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
138}
139
140#ifdef CONFIG_FSL_ESDHC
141struct fsl_esdhc_cfg usdhc_cfg[1] = {
142 {USDHC3_BASE_ADDR},
143};
144
145int board_mmc_getcd(struct mmc *mmc)
146{
147 gpio_direction_input(IMX_GPIO_NR(6, 15));
148 return !gpio_get_value(IMX_GPIO_NR(6, 15));
149}
150
151int board_mmc_init(bd_t *bis)
152{
153 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
154
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000155 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
Fabio Estevam7dd65452012-09-24 08:09:33 +0000156 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
157}
158#endif
159
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000160int mx6_rgmii_rework(struct phy_device *phydev)
161{
162 unsigned short val;
163
164 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
165 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
166 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
167 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
168
169 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
170 val &= 0xffe3;
171 val |= 0x18;
172 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
173
174 /* introduce tx clock delay */
175 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
176 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
177 val |= 0x0100;
178 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
179
180 return 0;
181}
182
183int board_phy_config(struct phy_device *phydev)
184{
185 mx6_rgmii_rework(phydev);
186
187 if (phydev->drv->config)
188 phydev->drv->config(phydev);
189
190 return 0;
191}
192
193int board_eth_init(bd_t *bis)
194{
195 int ret;
196
197 setup_iomux_enet();
198
199 ret = cpu_eth_init(bis);
200 if (ret)
201 printf("FEC MXC: %s:failed\n", __func__);
202
Fabio Estevame12408c2013-09-12 22:03:23 -0300203 return ret;
Fabio Estevamfe5ebe92012-09-25 08:43:57 +0000204}
205
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000206#define BOARD_REV_B 0x200
207#define BOARD_REV_A 0x100
208
209static int mx6sabre_rev(void)
210{
211 /*
212 * Get Board ID information from OCOTP_GP1[15:8]
213 * i.MX6Q ARD RevA: 0x01
214 * i.MX6Q ARD RevB: 0x02
215 */
216 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
Benoît Thébaudeau8f3ff112013-04-23 10:17:38 +0000217 struct fuse_bank *bank = &ocotp->bank[4];
218 struct fuse_bank4_regs *fuse =
219 (struct fuse_bank4_regs *)bank->fuse_regs;
220 int reg = readl(&fuse->gp1);
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000221 int ret;
222
223 switch (reg >> 8 & 0x0F) {
224 case 0x02:
225 ret = BOARD_REV_B;
226 break;
227 case 0x01:
228 default:
229 ret = BOARD_REV_A;
230 break;
231 }
232
233 return ret;
234}
235
Fabio Estevam7dd65452012-09-24 08:09:33 +0000236u32 get_board_rev(void)
237{
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000238 int rev = mx6sabre_rev();
239
240 return (get_cpu_rev() & ~(0xF << 8)) | rev;
Fabio Estevam7dd65452012-09-24 08:09:33 +0000241}
242
243int board_early_init_f(void)
244{
245 setup_iomux_uart();
246
247 return 0;
248}
249
250int board_init(void)
251{
252 /* address of boot parameters */
253 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
254
Renato Frias19578162013-05-13 18:01:12 +0000255 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
256 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
257 /* I2C 3 Steer */
258 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
259 imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
260 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
261
Renato Friasa1f67802013-05-13 18:01:13 +0000262 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
263 imx_iomux_v3_setup_multiple_pads(port_exp, ARRAY_SIZE(port_exp));
264
Fabio Estevam7dd65452012-09-24 08:09:33 +0000265 return 0;
266}
267
Otavio Salvador85449db2013-03-16 08:05:07 +0000268#ifdef CONFIG_CMD_BMODE
269static const struct boot_mode board_boot_modes[] = {
270 /* 4 bit bus width */
271 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
272 {NULL, 0},
273};
274#endif
275
276int board_late_init(void)
277{
278#ifdef CONFIG_CMD_BMODE
279 add_board_boot_modes(board_boot_modes);
280#endif
281
282 return 0;
283}
284
Fabio Estevam7dd65452012-09-24 08:09:33 +0000285int checkboard(void)
286{
Fabio Estevamdce67bd2012-10-02 11:20:12 +0000287 int rev = mx6sabre_rev();
288 char *revname;
289
290 switch (rev) {
291 case BOARD_REV_B:
292 revname = "B";
293 break;
294 case BOARD_REV_A:
295 default:
296 revname = "A";
297 break;
298 }
299
300 printf("Board: MX6Q-Sabreauto rev%s\n", revname);
Fabio Estevam7dd65452012-09-24 08:09:33 +0000301
302 return 0;
303}