| wdenk | affae2b | 2002-08-17 09:36:01 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Rich Ireland, Enterasys Networks, rireland@enterasys.com. |
| 4 | * |
| 5 | * See file CREDITS for list of people who contributed to this |
| 6 | * project. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; either version 2 of |
| 11 | * the License, or (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 21 | * MA 02111-1307 USA |
| 22 | * |
| 23 | */ |
| 24 | |
| 25 | #include <common.h> |
| 26 | #include <asm/processor.h> |
| 27 | #include <asm/mmu.h> |
| 28 | |
| 29 | int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) |
| 30 | { |
| 31 | switch (bat) { |
| 32 | case IBAT0: |
| 33 | mtspr (IBAT0L, lower); |
| 34 | mtspr (IBAT0U, upper); |
| 35 | break; |
| 36 | |
| 37 | case IBAT1: |
| 38 | mtspr (IBAT1L, lower); |
| 39 | mtspr (IBAT1U, upper); |
| 40 | break; |
| 41 | |
| 42 | case IBAT2: |
| 43 | mtspr (IBAT2L, lower); |
| 44 | mtspr (IBAT2U, upper); |
| 45 | break; |
| 46 | |
| 47 | case IBAT3: |
| 48 | mtspr (IBAT3L, lower); |
| 49 | mtspr (IBAT3U, upper); |
| 50 | break; |
| 51 | |
| 52 | case DBAT0: |
| 53 | mtspr (DBAT0L, lower); |
| 54 | mtspr (DBAT0U, upper); |
| 55 | break; |
| 56 | |
| 57 | case DBAT1: |
| 58 | mtspr (DBAT1L, lower); |
| 59 | mtspr (DBAT1U, upper); |
| 60 | break; |
| 61 | |
| 62 | case DBAT2: |
| 63 | mtspr (DBAT2L, lower); |
| 64 | mtspr (DBAT2U, upper); |
| 65 | break; |
| 66 | |
| 67 | case DBAT3: |
| 68 | mtspr (DBAT3L, lower); |
| 69 | mtspr (DBAT3U, upper); |
| 70 | break; |
| 71 | |
| 72 | default: |
| 73 | return (-1); |
| 74 | } |
| 75 | |
| 76 | return (0); |
| 77 | } |
| 78 | |
| 79 | int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) |
| 80 | { |
| 81 | unsigned long register u; |
| 82 | unsigned long register l; |
| 83 | |
| 84 | switch (bat) { |
| 85 | case IBAT0: |
| 86 | l = mfspr (IBAT0L); |
| 87 | u = mfspr (IBAT0U); |
| 88 | break; |
| 89 | |
| 90 | case IBAT1: |
| 91 | l = mfspr (IBAT1L); |
| 92 | u = mfspr (IBAT1U); |
| 93 | break; |
| 94 | |
| 95 | case IBAT2: |
| 96 | l = mfspr (IBAT2L); |
| 97 | u = mfspr (IBAT2U); |
| 98 | break; |
| 99 | |
| 100 | case IBAT3: |
| 101 | l = mfspr (IBAT3L); |
| 102 | u = mfspr (IBAT3U); |
| 103 | break; |
| 104 | |
| 105 | case DBAT0: |
| 106 | l = mfspr (DBAT0L); |
| 107 | u = mfspr (DBAT0U); |
| 108 | break; |
| 109 | |
| 110 | case DBAT1: |
| 111 | l = mfspr (DBAT1L); |
| 112 | u = mfspr (DBAT1U); |
| 113 | break; |
| 114 | |
| 115 | case DBAT2: |
| 116 | l = mfspr (DBAT2L); |
| 117 | u = mfspr (DBAT2U); |
| 118 | break; |
| 119 | |
| 120 | case DBAT3: |
| 121 | l = mfspr (DBAT3L); |
| 122 | u = mfspr (DBAT3U); |
| 123 | break; |
| 124 | |
| 125 | default: |
| 126 | return (-1); |
| 127 | } |
| 128 | |
| 129 | *upper = u; |
| 130 | *lower = l; |
| 131 | |
| 132 | return (0); |
| 133 | } |