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wdenk10767cc2004-05-13 13:23:58 +00001/*
wdenk1d6f9722004-09-09 17:44:35 +00002 * ueberarbeitet durch Christoph Seyfert
3 *
wdenk414eec32005-04-02 22:37:54 +00004 * (C) Copyright 2004-2005 DENX Software Engineering,
wdenk10767cc2004-05-13 13:23:58 +00005 * Wolfgang Grandegger <wg@denx.de>
6 * (C) Copyright 2003
7 * DAVE Srl
8 *
9 * http://www.dave-tech.it
10 * http://www.wawnet.biz
11 * mailto:info@wawnet.biz
12 *
13 * Credits: Stefan Roese, Wolfgang Denk
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31/*
32 * board/config.h - configuration options, board specific
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
39#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
40#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
41#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
42#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
43#endif
44
wdenk1d6f9722004-09-09 17:44:35 +000045/* Only one of the following two symbols must be defined (default is 25 MHz)
46 * CONFIG_PPCHAMELEON_CLK_25
47 * CONFIG_PPCHAMELEON_CLK_33
48 */
49#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50#define CONFIG_PPCHAMELEON_CLK_25
51#endif
52
53#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54#error "* Two external frequencies (SysClk) are defined! *"
55#endif
56
57#undef CONFIG_PPCHAMELEON_SMI712
58
wdenk10767cc2004-05-13 13:23:58 +000059/*
60 * Debug stuff
61 */
62#undef __DEBUG_START_FROM_SRAM__
63#define __DISABLE_MACHINE_EXCEPTION__
64
65#ifdef __DEBUG_START_FROM_SRAM__
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066#define CONFIG_SYS_DUMMY_FLASH_SIZE 1024*1024*4
wdenk10767cc2004-05-13 13:23:58 +000067#endif
68
69/*
70 * High Level Configuration Options
71 * (easy to change)
72 */
73
74#define CONFIG_405EP 1 /* This is a PPC405 CPU */
75#define CONFIG_4xx 1 /* ...member of PPC4xx family */
76#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
79#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
80
wdenk1d6f9722004-09-09 17:44:35 +000081#ifdef CONFIG_PPCHAMELEON_CLK_25
82# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
83#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
wdenk10767cc2004-05-13 13:23:58 +000084#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk1d6f9722004-09-09 17:44:35 +000085#else
86# error "* External frequency (SysClk) not defined! *"
87#endif
wdenk10767cc2004-05-13 13:23:58 +000088
wdenk1d6f9722004-09-09 17:44:35 +000089#define CONFIG_UART1_CONSOLE 1 /* Use second UART */
wdenk10767cc2004-05-13 13:23:58 +000090#define CONFIG_BAUDRATE 115200
91#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
92
wdenk1d6f9722004-09-09 17:44:35 +000093#define CONFIG_VERSION_VARIABLE 1 /* add version variable */
94#define CONFIG_IDENT_STRING "1"
95
wdenk10767cc2004-05-13 13:23:58 +000096#undef CONFIG_BOOTARGS
97
98/* Ethernet stuff */
99#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
wdenk1d6f9722004-09-09 17:44:35 +0000100#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
wdenke2ffd592004-12-31 09:32:47 +0000101#define CONFIG_HAS_ETH1
wdenk1d6f9722004-09-09 17:44:35 +0000102#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
wdenk10767cc2004-05-13 13:23:58 +0000103
104#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
wdenk10767cc2004-05-13 13:23:58 +0000106
107
108#undef CONFIG_EXT_PHY
wdenk1d6f9722004-09-09 17:44:35 +0000109#define CONFIG_NET_MULTI 1
wdenk10767cc2004-05-13 13:23:58 +0000110
111#define CONFIG_MII 1 /* MII PHY management */
112#ifndef CONFIG_EXT_PHY
stroesebf418862005-06-30 13:06:07 +0000113#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
stroese3c71f3e2005-07-01 15:53:57 +0000114#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
wdenk10767cc2004-05-13 13:23:58 +0000115#else
116#define CONFIG_PHY_ADDR 2 /* PHY address */
117#endif
118#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
119
wdenk414eec32005-04-02 22:37:54 +0000120#define CONFIG_TIMESTAMP /* Print image info with timestamp */
121
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500122
123/*
Jon Loeliger11799432007-07-10 09:02:57 -0500124 * BOOTP options
125 */
126#define CONFIG_BOOTP_BOOTFILESIZE
127#define CONFIG_BOOTP_BOOTPATH
128#define CONFIG_BOOTP_GATEWAY
129#define CONFIG_BOOTP_HOSTNAME
130
131
132/*
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500133 * Command line configuration.
134 */
135#include <config_cmd_default.h>
136
137#define CONFIG_CMD_DHCP
138#define CONFIG_CMD_ELF
139#define CONFIG_CMD_EEPROM
140#define CONFIG_CMD_I2C
141#define CONFIG_CMD_IRQ
142#define CONFIG_CMD_JFFS2
143#define CONFIG_CMD_MII
144#define CONFIG_CMD_NAND
145#define CONFIG_CMD_NFS
146#define CONFIG_CMD_SNTP
147
wdenk10767cc2004-05-13 13:23:58 +0000148
149#define CONFIG_MAC_PARTITION
150#define CONFIG_DOS_PARTITION
151
wdenk10767cc2004-05-13 13:23:58 +0000152#undef CONFIG_WATCHDOG /* watchdog disabled */
153
154#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
wdenk10767cc2004-05-13 13:23:58 +0000156
157#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
158
159/*
160 * Miscellaneous configurable options
161 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_LONGHELP /* undef to save memory */
163#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenk10767cc2004-05-13 13:23:58 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
166#ifdef CONFIG_SYS_HUSH_PARSER
167#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
wdenk10767cc2004-05-13 13:23:58 +0000168#endif
169
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500170#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200171#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk10767cc2004-05-13 13:23:58 +0000172#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk10767cc2004-05-13 13:23:58 +0000174#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
176#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
177#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk10767cc2004-05-13 13:23:58 +0000178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
wdenk10767cc2004-05-13 13:23:58 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
wdenk10767cc2004-05-13 13:23:58 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
184#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk10767cc2004-05-13 13:23:58 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_BASE_BAUD 691200
wdenk10767cc2004-05-13 13:23:58 +0000188
189/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_BAUDRATE_TABLE \
wdenk10767cc2004-05-13 13:23:58 +0000191 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
192 57600, 115200, 230400, 460800, 921600 }
193
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
195#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
wdenk10767cc2004-05-13 13:23:58 +0000196
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk10767cc2004-05-13 13:23:58 +0000198
199#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
200
201/*-----------------------------------------------------------------------
202 * NAND-FLASH stuff
203 *-----------------------------------------------------------------------
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_NAND0_BASE 0xFF400000
206#define CONFIG_SYS_NAND1_BASE 0xFF000000
207#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE }
Marian Balakowicz6db39702006-04-08 19:08:06 +0200208#define NAND_BIG_DELAY_US 25
wdenk10767cc2004-05-13 13:23:58 +0000209
210/* For CATcenter there is only NAND on the module */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
wdenk10767cc2004-05-13 13:23:58 +0000212#define NAND_NO_RB
213
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
215#define CONFIG_SYS_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
216#define CONFIG_SYS_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
217#define CONFIG_SYS_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
wdenk10767cc2004-05-13 13:23:58 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
220#define CONFIG_SYS_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
221#define CONFIG_SYS_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
222#define CONFIG_SYS_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
wdenk10767cc2004-05-13 13:23:58 +0000223
224
Marian Balakowicz6db39702006-04-08 19:08:06 +0200225#define MACRO_NAND_DISABLE_CE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000226{ \
Marian Balakowicz6db39702006-04-08 19:08:06 +0200227 switch((unsigned long)nandptr) \
wdenk10767cc2004-05-13 13:23:58 +0000228 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229 case CONFIG_SYS_NAND0_BASE: \
230 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000231 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232 case CONFIG_SYS_NAND1_BASE: \
233 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000234 break; \
235 } \
236} while(0)
237
Marian Balakowicz6db39702006-04-08 19:08:06 +0200238#define MACRO_NAND_ENABLE_CE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000239{ \
Marian Balakowicz6db39702006-04-08 19:08:06 +0200240 switch((unsigned long)nandptr) \
wdenk10767cc2004-05-13 13:23:58 +0000241 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242 case CONFIG_SYS_NAND0_BASE: \
243 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000244 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245 case CONFIG_SYS_NAND1_BASE: \
246 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CE); \
wdenk10767cc2004-05-13 13:23:58 +0000247 break; \
248 } \
249} while(0)
250
Marian Balakowicz6db39702006-04-08 19:08:06 +0200251#define MACRO_NAND_CTL_CLRALE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000252{ \
253 switch((unsigned long)nandptr) \
254 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255 case CONFIG_SYS_NAND0_BASE: \
256 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000257 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258 case CONFIG_SYS_NAND1_BASE: \
259 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000260 break; \
261 } \
262} while(0)
263
Marian Balakowicz6db39702006-04-08 19:08:06 +0200264#define MACRO_NAND_CTL_SETALE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000265{ \
266 switch((unsigned long)nandptr) \
267 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268 case CONFIG_SYS_NAND0_BASE: \
269 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000270 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200271 case CONFIG_SYS_NAND1_BASE: \
272 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_ALE); \
wdenk10767cc2004-05-13 13:23:58 +0000273 break; \
274 } \
275} while(0)
276
Marian Balakowicz6db39702006-04-08 19:08:06 +0200277#define MACRO_NAND_CTL_CLRCLE(nandptr) do \
wdenk10767cc2004-05-13 13:23:58 +0000278{ \
279 switch((unsigned long)nandptr) \
280 { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281 case CONFIG_SYS_NAND0_BASE: \
282 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND0_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000283 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284 case CONFIG_SYS_NAND1_BASE: \
285 out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_NAND1_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000286 break; \
287 } \
288} while(0)
289
Marian Balakowicz6db39702006-04-08 19:08:06 +0200290#define MACRO_NAND_CTL_SETCLE(nandptr) do { \
wdenk10767cc2004-05-13 13:23:58 +0000291 switch((unsigned long)nandptr) { \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 case CONFIG_SYS_NAND0_BASE: \
293 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND0_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000294 break; \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295 case CONFIG_SYS_NAND1_BASE: \
296 out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND1_CLE); \
wdenk10767cc2004-05-13 13:23:58 +0000297 break; \
298 } \
299} while(0)
300
301#ifdef NAND_NO_RB
302/* constant delay (see also tR in the datasheet) */
303#define NAND_WAIT_READY(nand) do { \
304 udelay(12); \
305} while (0)
306#else
307/* use the R/B pin */
308/* TBD */
309#endif
310
311#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
312#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
313#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
314#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
315
316/*-----------------------------------------------------------------------
317 * PCI stuff
318 *-----------------------------------------------------------------------
319 */
320#if 0 /* No PCI on CATcenter */
321#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
322#define PCI_HOST_FORCE 1 /* configure as pci host */
323#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
324
325#define CONFIG_PCI /* include pci support */
326#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
327#undef CONFIG_PCI_PNP /* do pci plug-and-play */
328 /* resource configuration */
329
330#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
331
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
333#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
334#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
wdenk1d6f9722004-09-09 17:44:35 +0000335
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
337#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
338#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
339#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
340#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
341#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
wdenk10767cc2004-05-13 13:23:58 +0000342#endif /* No PCI */
343
344/*-----------------------------------------------------------------------
345 * Start addresses for the final memory configuration
346 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk10767cc2004-05-13 13:23:58 +0000348 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_SDRAM_BASE 0x00000000
350#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
351#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
352#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
353#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
wdenk10767cc2004-05-13 13:23:58 +0000354
355/*
356 * For booting Linux, the board info and command line data
357 * have to be in the first 8 MB of memory, since this is
358 * the maximum mapped by the Linux kernel during initialization.
359 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200360#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk10767cc2004-05-13 13:23:58 +0000361/*-----------------------------------------------------------------------
362 * FLASH organization
363 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
365#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
wdenk10767cc2004-05-13 13:23:58 +0000366
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
368#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenk10767cc2004-05-13 13:23:58 +0000369
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
371#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
372#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
wdenk10767cc2004-05-13 13:23:58 +0000373/*
374 * The following defines are added for buggy IOP480 byte interface.
375 * All other boards should use the standard values (CPCI405 etc.)
376 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
378#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
379#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
wdenk10767cc2004-05-13 13:23:58 +0000380
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
wdenk10767cc2004-05-13 13:23:58 +0000382
wdenk10767cc2004-05-13 13:23:58 +0000383/*-----------------------------------------------------------------------
384 * Environment Variable setup
385 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200386#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200387#define CONFIG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
388#define CONFIG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
389#define CONFIG_ENV_ADDR_REDUND 0xFFFFA000
390#define CONFIG_ENV_SIZE_REDUND 0x2000
wdenk10767cc2004-05-13 13:23:58 +0000391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200393
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
395#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
wdenk10767cc2004-05-13 13:23:58 +0000396
397/*-----------------------------------------------------------------------
398 * I2C EEPROM (CAT24WC16) for environment
399 */
400#define CONFIG_HARD_I2C /* I2c with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
402#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk10767cc2004-05-13 13:23:58 +0000403
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
405#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
wdenk10767cc2004-05-13 13:23:58 +0000406/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200407/*#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
408#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
wdenk10767cc2004-05-13 13:23:58 +0000409 /* 16 byte page write mode using*/
410 /* last 4 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200411#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
wdenk10767cc2004-05-13 13:23:58 +0000412
413/*-----------------------------------------------------------------------
414 * Cache Configuration
415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenk10767cc2004-05-13 13:23:58 +0000417 /* have only 8kB, 16kB is save here */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200418#define CONFIG_SYS_CACHELINE_SIZE 32 /* ... */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500419#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk10767cc2004-05-13 13:23:58 +0000421#endif
422
423/*
424 * Init Memory Controller:
425 *
426 * BR0/1 and OR0/1 (FLASH)
427 */
428
429#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
430
431/*-----------------------------------------------------------------------
432 * External Bus Controller (EBC) Setup
433 */
434
435/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_EBC_PB0AP 0x92015480
437#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
wdenk10767cc2004-05-13 13:23:58 +0000438
439/* Memory Bank 1 (External SRAM) initialization */
440/* Since this must replace NOR Flash, we use the same settings for CS0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200441#define CONFIG_SYS_EBC_PB1AP 0x92015480
442#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
wdenk10767cc2004-05-13 13:23:58 +0000443
444/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200445#define CONFIG_SYS_EBC_PB2AP 0x92015480
446#define CONFIG_SYS_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
wdenk10767cc2004-05-13 13:23:58 +0000447
448/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_EBC_PB3AP 0x92015480
450#define CONFIG_SYS_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
wdenk10767cc2004-05-13 13:23:58 +0000451
wdenk1d6f9722004-09-09 17:44:35 +0000452#ifdef CONFIG_PPCHAMELEON_SMI712
453/*
454 * Video console (graphic: SMI LynxEM)
455 */
456#define CONFIG_VIDEO
457#define CONFIG_CFB_CONSOLE
458#define CONFIG_VIDEO_SMI_LYNXEM
459#define CONFIG_VIDEO_LOGO
460/*#define CONFIG_VIDEO_BMP_LOGO*/
461#define CONFIG_CONSOLE_EXTRA_INFO
462#define CONFIG_VGA_AS_SINGLE_DEVICE
463/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200464#define CONFIG_SYS_ISA_IO 0xE8000000
Marcel Ziswiler7817cb22007-12-30 03:30:46 +0100465/* see also drivers/video/videomodes.c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x303
wdenk10767cc2004-05-13 13:23:58 +0000467#endif
468
469/*-----------------------------------------------------------------------
470 * FPGA stuff
471 */
472/* FPGA internal regs */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_FPGA_MODE 0x00
474#define CONFIG_SYS_FPGA_STATUS 0x02
475#define CONFIG_SYS_FPGA_TS 0x04
476#define CONFIG_SYS_FPGA_TS_LOW 0x06
477#define CONFIG_SYS_FPGA_TS_CAP0 0x10
478#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
479#define CONFIG_SYS_FPGA_TS_CAP1 0x14
480#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
481#define CONFIG_SYS_FPGA_TS_CAP2 0x18
482#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
483#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
484#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
wdenk10767cc2004-05-13 13:23:58 +0000485
486/* FPGA Mode Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200487#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
488#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
489#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
490#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
wdenk10767cc2004-05-13 13:23:58 +0000491
492/* FPGA Status Reg */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
494#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
495#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
496#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
497#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
wdenk10767cc2004-05-13 13:23:58 +0000498
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200499#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
500#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
wdenk10767cc2004-05-13 13:23:58 +0000501
502/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
504#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
505#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
506#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
507#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
wdenk10767cc2004-05-13 13:23:58 +0000508
509/*-----------------------------------------------------------------------
510 * Definitions for initial stack pointer and data area (in data cache)
511 */
512/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200513#define CONFIG_SYS_TEMP_STACK_OCM 1
wdenk10767cc2004-05-13 13:23:58 +0000514
515/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
517#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
518#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
519#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
wdenk10767cc2004-05-13 13:23:58 +0000520
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200521#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
522#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
523#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk10767cc2004-05-13 13:23:58 +0000524
525/*-----------------------------------------------------------------------
526 * Definitions for GPIO setup (PPC405EP specific)
527 *
528 * GPIO0[0] - External Bus Controller BLAST output
529 * GPIO0[1-9] - Instruction trace outputs -> GPIO
530 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
531 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
532 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
533 * GPIO0[24-27] - UART0 control signal inputs/outputs
534 * GPIO0[28-29] - UART1 data signal input/output
535 * GPIO0[30] - EMAC0 input
536 * GPIO0[31] - EMAC1 reject packet as output
537 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200538#define CONFIG_SYS_GPIO0_OSRL 0x40000550
539#define CONFIG_SYS_GPIO0_OSRH 0x00000110
540#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
541/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/
542#define CONFIG_SYS_GPIO0_ISR1H 0x15555444
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200543#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200544#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200545#define CONFIG_SYS_GPIO0_TCR 0xF7FF8014
wdenk10767cc2004-05-13 13:23:58 +0000546
547/*
548 * Internal Definitions
549 *
550 * Boot Flags
551 */
552#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
553#define BOOTFLAG_WARM 0x02 /* Software reboot */
554
555
556#define CONFIG_NO_SERIAL_EEPROM
557
558/*--------------------------------------------------------------------*/
559
560#ifdef CONFIG_NO_SERIAL_EEPROM
561
562/*
563!-----------------------------------------------------------------------
564! Defines for entry options.
565! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
566! are plugged in the board will be utilized as non-ECC DIMMs.
567!-----------------------------------------------------------------------
568*/
569#undef AUTO_MEMORY_CONFIG
570#define DIMM_READ_ADDR 0xAB
571#define DIMM_WRITE_ADDR 0xAA
572
wdenk10767cc2004-05-13 13:23:58 +0000573#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
574#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
575#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
576#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
577#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
578#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
579#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
580#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
581#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
582#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
583
584/* Defines for CPC0_PLLMR1 Register fields */
585#define PLL_ACTIVE 0x80000000
586#define CPC0_PLLMR1_SSCS 0x80000000
587#define PLL_RESET 0x40000000
588#define CPC0_PLLMR1_PLLR 0x40000000
589 /* Feedback multiplier */
590#define PLL_FBKDIV 0x00F00000
591#define CPC0_PLLMR1_FBDV 0x00F00000
592#define PLL_FBKDIV_16 0x00000000
593#define PLL_FBKDIV_1 0x00100000
594#define PLL_FBKDIV_2 0x00200000
595#define PLL_FBKDIV_3 0x00300000
596#define PLL_FBKDIV_4 0x00400000
597#define PLL_FBKDIV_5 0x00500000
598#define PLL_FBKDIV_6 0x00600000
599#define PLL_FBKDIV_7 0x00700000
600#define PLL_FBKDIV_8 0x00800000
601#define PLL_FBKDIV_9 0x00900000
602#define PLL_FBKDIV_10 0x00A00000
603#define PLL_FBKDIV_11 0x00B00000
604#define PLL_FBKDIV_12 0x00C00000
605#define PLL_FBKDIV_13 0x00D00000
606#define PLL_FBKDIV_14 0x00E00000
607#define PLL_FBKDIV_15 0x00F00000
608 /* Forward A divisor */
609#define PLL_FWDDIVA 0x00070000
610#define CPC0_PLLMR1_FWDVA 0x00070000
611#define PLL_FWDDIVA_8 0x00000000
612#define PLL_FWDDIVA_7 0x00010000
613#define PLL_FWDDIVA_6 0x00020000
614#define PLL_FWDDIVA_5 0x00030000
615#define PLL_FWDDIVA_4 0x00040000
616#define PLL_FWDDIVA_3 0x00050000
617#define PLL_FWDDIVA_2 0x00060000
618#define PLL_FWDDIVA_1 0x00070000
619 /* Forward B divisor */
620#define PLL_FWDDIVB 0x00007000
621#define CPC0_PLLMR1_FWDVB 0x00007000
622#define PLL_FWDDIVB_8 0x00000000
623#define PLL_FWDDIVB_7 0x00001000
624#define PLL_FWDDIVB_6 0x00002000
625#define PLL_FWDDIVB_5 0x00003000
626#define PLL_FWDDIVB_4 0x00004000
627#define PLL_FWDDIVB_3 0x00005000
628#define PLL_FWDDIVB_2 0x00006000
629#define PLL_FWDDIVB_1 0x00007000
630 /* PLL tune bits */
631#define PLL_TUNE_MASK 0x000003FF
632#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
633#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
634#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
635#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
636#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
637#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
638#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
639
640/* Defines for CPC0_PLLMR0 Register fields */
641 /* CPU divisor */
642#define PLL_CPUDIV 0x00300000
643#define CPC0_PLLMR0_CCDV 0x00300000
644#define PLL_CPUDIV_1 0x00000000
645#define PLL_CPUDIV_2 0x00100000
646#define PLL_CPUDIV_3 0x00200000
647#define PLL_CPUDIV_4 0x00300000
648 /* PLB divisor */
649#define PLL_PLBDIV 0x00030000
650#define CPC0_PLLMR0_CBDV 0x00030000
651#define PLL_PLBDIV_1 0x00000000
652#define PLL_PLBDIV_2 0x00010000
653#define PLL_PLBDIV_3 0x00020000
654#define PLL_PLBDIV_4 0x00030000
655 /* OPB divisor */
656#define PLL_OPBDIV 0x00003000
657#define CPC0_PLLMR0_OPDV 0x00003000
658#define PLL_OPBDIV_1 0x00000000
659#define PLL_OPBDIV_2 0x00001000
660#define PLL_OPBDIV_3 0x00002000
661#define PLL_OPBDIV_4 0x00003000
662 /* EBC divisor */
663#define PLL_EXTBUSDIV 0x00000300
664#define CPC0_PLLMR0_EPDV 0x00000300
665#define PLL_EXTBUSDIV_2 0x00000000
666#define PLL_EXTBUSDIV_3 0x00000100
667#define PLL_EXTBUSDIV_4 0x00000200
668#define PLL_EXTBUSDIV_5 0x00000300
669 /* MAL divisor */
670#define PLL_MALDIV 0x00000030
671#define CPC0_PLLMR0_MPDV 0x00000030
672#define PLL_MALDIV_1 0x00000000
673#define PLL_MALDIV_2 0x00000010
674#define PLL_MALDIV_3 0x00000020
675#define PLL_MALDIV_4 0x00000030
676 /* PCI divisor */
677#define PLL_PCIDIV 0x00000003
678#define CPC0_PLLMR0_PPFD 0x00000003
679#define PLL_PCIDIV_1 0x00000000
680#define PLL_PCIDIV_2 0x00000001
681#define PLL_PCIDIV_3 0x00000002
682#define PLL_PCIDIV_4 0x00000003
683
wdenk1d6f9722004-09-09 17:44:35 +0000684#ifdef CONFIG_PPCHAMELEON_CLK_25
685/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
686#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
687 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
688 PLL_MALDIV_1 | PLL_PCIDIV_4)
689#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
690 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
691 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
692
693#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
694 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
695 PLL_MALDIV_1 | PLL_PCIDIV_4)
696#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
697 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
698 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
699
700#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
701 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
702 PLL_MALDIV_1 | PLL_PCIDIV_4)
703#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
704 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
705 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
706
707#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
708 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
709 PLL_MALDIV_1 | PLL_PCIDIV_2)
710#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
711 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
712 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
713
714#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
715
wdenk10767cc2004-05-13 13:23:58 +0000716/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
wdenk1d6f9722004-09-09 17:44:35 +0000717#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
718 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000719 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000720#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
721 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
wdenk10767cc2004-05-13 13:23:58 +0000722 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000723
724#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
725 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000726 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000727#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
728 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000729 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000730
731#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
732 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000733 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000734#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
735 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000736 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000737
738#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
739 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000740 PLL_MALDIV_1 | PLL_PCIDIV_2)
wdenk1d6f9722004-09-09 17:44:35 +0000741#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
742 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000743 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
744
wdenk1d6f9722004-09-09 17:44:35 +0000745#else
746#error "* External frequency (SysClk) not defined! *"
747#endif
748
wdenk10767cc2004-05-13 13:23:58 +0000749#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
750/* Model HI */
wdenk1d6f9722004-09-09 17:44:35 +0000751#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
752#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200753#define CONFIG_SYS_OPB_FREQ 55555555
wdenk10767cc2004-05-13 13:23:58 +0000754/* Model ME */
755#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
wdenk1d6f9722004-09-09 17:44:35 +0000756#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
757#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200758#define CONFIG_SYS_OPB_FREQ 66666666
wdenk10767cc2004-05-13 13:23:58 +0000759#else
760/* Model BA (default) */
wdenk1d6f9722004-09-09 17:44:35 +0000761#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
762#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200763#define CONFIG_SYS_OPB_FREQ 66666666
wdenk10767cc2004-05-13 13:23:58 +0000764#endif
765
766#endif /* CONFIG_NO_SERIAL_EEPROM */
767
768#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk10767cc2004-05-13 13:23:58 +0000769#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
770
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200771/*
772 * JFFS2 partitions
773 *
774 */
775/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100776#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200777#define CONFIG_JFFS2_DEV "nand"
778#define CONFIG_JFFS2_PART_SIZE 0x00200000
779#define CONFIG_JFFS2_PART_OFFSET 0x00000000
780
781/* mtdparts command line support
782 *
783 * Note: fake mtd_id used, no linux mtd map file
784 */
785/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100786#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200787#define MTDIDS_DEFAULT "nand0=catcenter"
788#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
789*/
790
wdenk10767cc2004-05-13 13:23:58 +0000791#endif /* __CONFIG_H */