blob: 2e38c12baff72bf3863070ba6355ce7166936b56 [file] [log] [blame]
Heiko Schocher67fa8c22010-02-22 16:43:02 +05301/*
2 * (C) Copyright 2009
3 * Marvell Semiconductor <www.marvell.com>
4 * Prafulla Wadaskar <prafulla@marvell.com>
5 *
6 * (C) Copyright 2009
7 * Stefan Roese, DENX Software Engineering, sr@denx.de.
8 *
Heiko Schocherb11f53f2011-03-15 16:52:29 +01009 * (C) Copyright 2010-2011
10 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
11 *
Heiko Schocher67fa8c22010-02-22 16:43:02 +053012 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
28 * MA 02110-1301 USA
29 */
30
Heiko Schocherb11f53f2011-03-15 16:52:29 +010031/*
32 * for linking errors see
33 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
34 */
Heiko Schocher67fa8c22010-02-22 16:43:02 +053035
36#ifndef _CONFIG_KM_ARM_H
37#define _CONFIG_KM_ARM_H
38
39/*
40 * High Level Configuration Options (easy to change)
41 */
42#define CONFIG_MARVELL
43#define CONFIG_ARM926EJS /* Basic Architecture */
44#define CONFIG_FEROCEON_88FR131 /* CPU Core subversion */
45#define CONFIG_KIRKWOOD /* SOC Family Name */
46#define CONFIG_KW88F6281 /* SOC Name */
Holger Brunck802d9962011-03-14 15:31:19 +010047#define CONFIG_MACH_KM_KIRKWOOD /* Machine type */
Heiko Schocher67fa8c22010-02-22 16:43:02 +053048
49/* include common defines/options for all Keymile boards */
50#include "keymile-common.h"
Holger Brunckde3ad132011-03-14 16:01:04 +010051
52#define CONFIG_ENV_SIZE (128 << 10) /* NAND chip block size */
53#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
54#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
55#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
56
57/* pseudo-non volatile RAM [hex] */
58#define CONFIG_KM_PNVRAM 0x80000
59/* physical RAM MTD size [hex] */
60#define CONFIG_KM_PHRAM 0x17F000
61
62#define CONFIG_KM_CRAMFS_ADDR 0x2400000
63#define CONFIG_KM_KERNEL_ADDR 0x2000000 /* 4096KBytes */
64
65#define CONFIG_KM_DEF_ENV_CPU \
66 "addmtdparts=setenv bootargs ${bootargs} ${mtdparts}\0" \
67 "boot=bootm ${actual_kernel_addr} - -\0" \
68 "cramfsloadfdt=echo \\\\c\0" \
69 "tftpfdt=echo \\\\c\0" \
70 CONFIG_KM_DEF_ENV_UPDATE \
71 ""
72
73
Heiko Schocher67fa8c22010-02-22 16:43:02 +053074
75#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
76#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
77#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
78#undef CONFIG_KIRKWOOD_PCIE_INIT /* Disable PCIE Port0 for kernel */
79#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
80
81#define CONFIG_MISC_INIT_R
82
83/*
84 * NS16550 Configuration
85 */
86#define CONFIG_SYS_NS16550
87#define CONFIG_SYS_NS16550_SERIAL
88#define CONFIG_SYS_NS16550_REG_SIZE (-4)
89#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
90#define CONFIG_SYS_NS16550_COM1 KW_UART0_BASE
91
92/*
93 * Serial Port configuration
94 * The following definitions let you select what serial you want to use
95 * for your console driver.
96 */
97
98#define CONFIG_CONS_INDEX 1 /* Console on UART0 */
99
100/*
101 * For booting Linux, the board info and command line data
102 * have to be in the first 8 MB of memory, since this is
103 * the maximum mapped by the Linux kernel during initialization.
104 */
105#define CONFIG_BOOTMAPSZ (8 << 20) /* Initial Memmap for Linux */
106#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
107#define CONFIG_INITRD_TAG /* enable INITRD tag */
108#define CONFIG_SETUP_MEMORY_TAGS /* enable memory tag */
109
110/*
111 * Commands configuration
112 */
113#define CONFIG_CMD_ELF
114#define CONFIG_CMD_MTDPARTS
115#define CONFIG_CMD_NAND
116#define CONFIG_CMD_NFS
117
118/*
119 * Without NOR FLASH we need this
120 */
121#define CONFIG_SYS_NO_FLASH
122#undef CONFIG_CMD_FLASH
123#undef CONFIG_CMD_IMLS
124
125/*
126 * NAND Flash configuration
127 */
128#define CONFIG_SYS_MAX_NAND_DEVICE 1
129#define NAND_MAX_CHIPS 1
130#define CONFIG_NAND_KIRKWOOD
131#define CONFIG_SYS_NAND_BASE 0xd8000000
132
133#define BOOTFLASH_START 0x0
134
135#define CONFIG_KM_CONSOLE_TTY "ttyS0"
136
137/* size in bytes reserved for initial data */
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530138
139/*
140 * Other required minimal configurations
141 */
142#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
143#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
144#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
145#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
146#define CONFIG_NR_DRAM_BANKS 4
147#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
148#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
149
150/*
151 * Ethernet Driver configuration
152 */
153#define CONFIG_NETCONSOLE /* include NetConsole support */
154#define CONFIG_NET_MULTI /* specify more that one ports available */
155#define CONFIG_MII /* expose smi ove miiphy interface */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200156#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530157#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200158#define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530159#define CONFIG_PHY_BASE_ADR 0
160#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
161#define CONFIG_RESET_PHY_R /* use reset_phy() to init 88E1118 PHY */
162
163/*
164 * UBI related stuff
165 */
166#define CONFIG_SYS_USE_UBI
167
168/*
169 * I2C related stuff
170 */
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530171#define CONFIG_SOFT_I2C /* I2C bit-banged */
172
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530173#define CONFIG_KIRKWOOD_GPIO /* Enable GPIO Support */
174#if defined(CONFIG_SOFT_I2C)
175#ifndef __ASSEMBLY__
176#include <asm/arch-kirkwood/gpio.h>
177extern void __set_direction(unsigned pin, int high);
178void set_sda (int state);
179void set_scl (int state);
180int get_sda (void);
181int get_scl (void);
182#define SUEN3_SDA_PIN 8
183#define SUEN3_SCL_PIN 9
184#define SUEN3_ENV_WP 38
185
186#define I2C_ACTIVE __set_direction(SUEN3_SDA_PIN, 0)
187#define I2C_TRISTATE __set_direction(SUEN3_SDA_PIN, 1)
188#define I2C_READ (kw_gpio_get_value(SUEN3_SDA_PIN) ? 1 : 0)
189#define I2C_SDA(bit) kw_gpio_set_value(SUEN3_SDA_PIN, bit);
190#define I2C_SCL(bit) kw_gpio_set_value(SUEN3_SCL_PIN, bit);
191#endif
192
193#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */
194#define I2C_SOFT_DECLARATIONS
195
196#define CONFIG_SYS_I2C_SLAVE 0x0
197#define CONFIG_SYS_I2C_SPEED 100000
198#endif
199
200#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
201#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
202
Heiko Schocher331a30d2011-02-22 08:30:46 +0100203/*
204 * Environment variables configurations
205 */
206#define CONFIG_ENV_IS_IN_EEPROM /* use EEPROM for environment vars */
207#define CONFIG_SYS_DEF_EEPROM_ADDR 0x50
208#define CONFIG_ENV_EEPROM_IS_ON_I2C
209#define CONFIG_SYS_EEPROM_WREN
210#define CONFIG_ENV_OFFSET 0x0 /* no bracets! */
211#undef CONFIG_ENV_SIZE
212#define CONFIG_ENV_SIZE (0x2000 - CONFIG_ENV_OFFSET)
213#define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0"
214
215/* offset redund: (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) */
216#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
217#define CONFIG_ENV_OFFSET_REDUND 0x2000 /* no bracets! */
218#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
219
220#define CONFIG_CMD_SF
221
222#define CONFIG_SPI_FLASH
223#define CONFIG_HARD_SPI
224#define CONFIG_KIRKWOOD_SPI
225#define CONFIG_SPI_FLASH_STMICRO
226#define CONFIG_ENV_SPI_BUS 0
227#define CONFIG_ENV_SPI_CS 0
228#define CONFIG_ENV_SPI_MAX_HZ 50000000 /* 50Mhz */
229
230#define FLASH_GPIO_PIN 0x00010000
231
232#define MTDIDS_DEFAULT "nand0=orion_nand"
233/* test-only: partitioning needs some tuning, this is just for tests */
234#define MTDPARTS_DEFAULT "mtdparts=" \
235 "orion_nand:" \
236 "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
237
238#define CONFIG_KM_DEF_ENV_UPDATE \
239 "update=" \
240 "spi on;sf probe 0;sf erase 0 50000;" \
241 "sf write ${u-boot_addr_r} 0 ${filesize};" \
242 "spi off\0"
243
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530244#if defined(CONFIG_SYS_NO_FLASH)
245#define CONFIG_KM_UBI_PARTITION_NAME "ubi0"
246#undef CONFIG_FLASH_CFI_MTD
247#undef CONFIG_JFFS2_CMDLINE
248#endif
249
Heiko Schochera784c012010-09-22 14:06:33 +0200250/* additions for new relocation code, must be added to all boards */
Heiko Schocherab86f722010-09-17 13:10:42 +0200251#define CONFIG_SYS_SDRAM_BASE 0x00000000
Heiko Schocher6b0ccc32010-10-20 19:33:26 +0530252/* Kirkwood has 2k of Security SRAM, use it for SP */
253#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
254/* Do early setups now in board_init_f() */
255#define CONFIG_BOARD_EARLY_INIT_F
Heiko Schocher67fa8c22010-02-22 16:43:02 +0530256#endif /* _CONFIG_KM_ARM_H */