blob: 620d270893e4338f94757d2347f2662e88102b8c [file] [log] [blame]
Wolfgang Denk70a20472005-09-25 15:59:01 +02001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * Copied from lubbock.h
10 *
11 * (C) Copyright 2004
12 * BEC Systems <http://bec-systems.com>
13 * Cliff Brake <cliff.brake@gmail.com>
14 * Configuation settings for the Accelent/Vibren PXA255 IDP
15 *
16 * See file CREDITS for list of people who contributed to this
17 * project.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version.
23 *
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
28 *
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38#include <asm/arch/pxa-regs.h>
39
40/*
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020041 * If we are developing, we might want to start U-Boot from RAM
Wolfgang Denk70a20472005-09-25 15:59:01 +020042 * so we MUST NOT initialize critical regs like mem-timing ...
43 */
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020044#undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */
Marek Vasut65bd6a92010-10-20 21:20:07 +020045#define CONFIG_SYS_TEXT_BASE 0x0
Wolfgang Denk70a20472005-09-25 15:59:01 +020046
47/*
48 * define the following to enable debug blinks. A debug blink function
49 * must be defined in memsetup.S
50 */
51#undef DEBUG_BLINK_ENABLE
52#undef DEBUG_BLINKC_ENABLE
53
54/*
55 * High Level Configuration Options
56 * (easy to change)
57 */
58#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
59
60#undef CONFIG_LCD
61#ifdef CONFIG_LCD
62#define CONFIG_SHARP_LM8V31
63#endif
64
65#define CONFIG_MMC 1
Marcel Ziswiler2a4741d2007-10-19 00:25:33 +020066#define CONFIG_DOS_PARTITION 1
Helmut Raiger9660e442011-10-20 04:19:47 +000067#define CONFIG_BOARD_LATE_INIT
Wolfgang Denk70a20472005-09-25 15:59:01 +020068
69#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
70
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020071/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000072#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020073
Wolfgang Denk70a20472005-09-25 15:59:01 +020074/*
75 * Size of malloc() pool
76 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
Wolfgang Denk70a20472005-09-25 15:59:01 +020078
79/*
80 * PXA250 IDP memory map information
81 */
82
83#define IDP_CS5_ETH_OFFSET 0x03400000
84
85
86/*
87 * Hardware drivers
88 */
Ben Warren7194ab82009-10-04 22:37:03 -070089#define CONFIG_SMC91111
Wolfgang Denk70a20472005-09-25 15:59:01 +020090#define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300)
91#define CONFIG_SMC_USE_32_BIT 1
92/* #define CONFIG_SMC_USE_IOFUNCS */
93
94/* the following has to be set high -- suspect something is wrong with
95 * with the tftp timeout routines. FIXME!!!
96 */
97#define CONFIG_NET_RETRY_COUNT 100
98
99/*
100 * select serial console configuration
101 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +0200102#define CONFIG_PXA_SERIAL
Wolfgang Denk70a20472005-09-25 15:59:01 +0200103#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
104
105/* allow to overwrite serial and ethaddr */
106#define CONFIG_ENV_OVERWRITE
107
108#define CONFIG_BAUDRATE 115200
109
Wolfgang Denk70a20472005-09-25 15:59:01 +0200110
Jon Loeliger26a34562007-07-04 22:33:17 -0500111/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500112 * BOOTP options
113 */
114#define CONFIG_BOOTP_BOOTFILESIZE
115#define CONFIG_BOOTP_BOOTPATH
116#define CONFIG_BOOTP_GATEWAY
117#define CONFIG_BOOTP_HOSTNAME
118
119
120/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500121 * Command line configuration.
122 */
123#include <config_cmd_default.h>
124
Jon Loeliger26a34562007-07-04 22:33:17 -0500125#define CONFIG_CMD_FAT
126#define CONFIG_CMD_DHCP
127
Wolfgang Denk70a20472005-09-25 15:59:01 +0200128#define CONFIG_BOOTDELAY 3
129#define CONFIG_BOOTCOMMAND "bootm 40000"
130#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200"
Wolfgang Denk25dbe982008-07-13 23:07:35 +0200131
132#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
133#define CONFIG_SETUP_MEMORY_TAGS 1
134/* #define CONFIG_INITRD_TAG 1 */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200135
136/*
137 * Current memory map for Vibren supplied Linux images:
138 *
139 * Flash:
140 * 0 - 0x3ffff (size = 0x40000): bootloader
141 * 0x40000 - 0x13ffff (size = 0x100000): kernel
142 * 0x140000 - 0x1f3ffff (size = 0x1e00000): jffs
143 *
144 * RAM:
145 * 0xa0008000 - kernel is loaded
146 * 0xa3000000 - Uboot runs (48MB into RAM)
147 *
148 */
149
150#define CONFIG_EXTRA_ENV_SETTINGS \
151 "prog_boot_mmc=" \
152 "mw.b 0xa0000000 0xff 0x40000; " \
153 "if mmcinit && " \
154 "fatload mmc 0 0xa0000000 u-boot.bin; " \
155 "then " \
156 "protect off 0x0 0x3ffff; " \
157 "erase 0x0 0x3ffff; " \
158 "cp.b 0xa0000000 0x0 0x40000; " \
159 "reset;" \
160 "fi\0" \
161 "prog_uzImage_mmc=" \
162 "mw.b 0xa0000000 0xff 0x100000; " \
163 "if mmcinit && " \
164 "fatload mmc 0 0xa0000000 uzImage; " \
165 "then " \
166 "protect off 0x40000 0xfffff; " \
167 "erase 0x40000 0xfffff; " \
168 "cp.b 0xa0000000 0x40000 0x100000; " \
169 "fi\0" \
170 "prog_jffs_mmc=" \
171 "mw.b 0xa0000000 0xff 0x1e00000; " \
172 "if mmcinit && " \
173 "fatload mmc 0 0xa0000000 root.jffs; " \
174 "then " \
175 "protect off 0x140000 0x1f3ffff; " \
176 "erase 0x140000 0x1f3ffff; " \
177 "cp.b 0xa0000000 0x140000 0x1e00000; " \
178 "fi\0" \
179 "boot_mmc=" \
180 "if mmcinit && " \
181 "fatload mmc 0 0xa1000000 uzImage && " \
182 "then " \
183 "bootm 0xa1000000; " \
184 "fi\0" \
185 "prog_boot_net=" \
186 "mw.b 0xa0000000 0xff 0x100000; " \
187 "if bootp 0xa0000000 u-boot.bin; " \
188 "then " \
189 "protect off 0x0 0x3ffff; " \
190 "erase 0x0 0x3ffff; " \
191 "cp.b 0xa0000000 0x0 0x40000; " \
192 "reset; " \
193 "fi\0" \
194 "prog_uzImage_net=" \
195 "mw.b 0xa0000000 0xff 0x100000; " \
196 "if bootp 0xa0000000 uzImage; " \
197 "then " \
198 "protect off 0x40000 0xfffff; " \
199 "erase 0x40000 0xfffff; " \
200 "cp.b 0xa0000000 0x40000 0x100000; " \
201 "fi\0" \
202 "prog_jffs_net=" \
203 "mw.b 0xa0000000 0xff 0x1e00000; " \
204 "if bootp 0xa0000000 root.jffs; " \
205 "then " \
206 "protect off 0x140000 0x1f3ffff; " \
207 "erase 0x140000 0x1f3ffff; " \
208 "cp.b 0xa0000000 0x140000 0x1e00000; " \
209 "fi\0"
210
211
212/* "erase_env=" */
213/* "protect off" */
214
215
Jon Loeliger26a34562007-07-04 22:33:17 -0500216#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200217#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
218#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
219#endif
220
221/*
222 * Miscellaneous configurable options
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_HUSH_PARSER 1
225#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Wolfgang Denk70a20472005-09-25 15:59:01 +0200226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_LONGHELP /* undef to save memory */
228#ifdef CONFIG_SYS_HUSH_PARSER
229#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200230#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200232#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
234#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
235#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
236#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
237#define CONFIG_SYS_DEVICE_NULLDEV 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200238
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
240#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200241
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200243
Micha Kalfon94a33122009-02-11 19:50:11 +0200244#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200246
247#define RTC 1 /* enable 32KHz osc */
248
249 /* valid baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200250#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Wolfgang Denk70a20472005-09-25 15:59:01 +0200251
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100252#ifdef CONFIG_MMC
253#define CONFIG_PXA_MMC
254#define CONFIG_CMD_MMC
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_MMC_BASE 0xF0000000
Jean-Christophe PLAGNIOL-VILLARDb03d92e2009-02-20 03:47:50 +0100256#endif
Wolfgang Denk70a20472005-09-25 15:59:01 +0200257
258/*
259 * Stack sizes
260 *
261 * The stack sizes are set up in start.S using the settings below
262 */
263#define CONFIG_STACKSIZE (128*1024) /* regular stack */
264#ifdef CONFIG_USE_IRQ
265#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
266#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
267#endif
268
269/*
270 * Physical Memory Map
271 */
Marek Vasut65bd6a92010-10-20 21:20:07 +0200272#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200273#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
274#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
275#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
276#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
277#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
278#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
279#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
280#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
281
282#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
283#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */
284#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */
285#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */
286#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_DRAM_BASE 0xa0000000
289#define CONFIG_SYS_DRAM_SIZE 0x04000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200292
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200293#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200294#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200295
Wolfgang Denk70a20472005-09-25 15:59:01 +0200296/*
297 * GPIO settings
298 */
299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_GAFR0_L_VAL 0x80001005
301#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012
302#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558
303#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a
304#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
305#define CONFIG_SYS_GAFR2_U_VAL 0x2
306#define CONFIG_SYS_GPCR0_VAL 0x1800400
307#define CONFIG_SYS_GPCR1_VAL 0x0
308#define CONFIG_SYS_GPCR2_VAL 0x0
309#define CONFIG_SYS_GPDR0_VAL 0xc1818440
310#define CONFIG_SYS_GPDR1_VAL 0xfcffab82
311#define CONFIG_SYS_GPDR2_VAL 0x1ffff
312#define CONFIG_SYS_GPSR0_VAL 0x8000
313#define CONFIG_SYS_GPSR1_VAL 0x3f0002
314#define CONFIG_SYS_GPSR2_VAL 0x1c000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_PSSR_VAL 0x20
Wolfgang Denk70a20472005-09-25 15:59:01 +0200317
Marek Vasut65bd6a92010-10-20 21:20:07 +0200318#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10
319#define CONFIG_SYS_CKEN 0x0
320
Wolfgang Denk70a20472005-09-25 15:59:01 +0200321/*
322 * Memory settings
323 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2
325#define CONFIG_SYS_MSC1_VAL 0x43AC494C
326#define CONFIG_SYS_MSC2_VAL 0x39D449D4
327#define CONFIG_SYS_MDCNFG_VAL 0x090009C9
328#define CONFIG_SYS_MDREFR_VAL 0x0085C017
329#define CONFIG_SYS_MDMRS_VAL 0x00220022
Marek Vasut65bd6a92010-10-20 21:20:07 +0200330#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
331#define CONFIG_SYS_SXCNFG_VAL 0x00000000
Wolfgang Denk70a20472005-09-25 15:59:01 +0200332
333/*
334 * PCMCIA and CF Interfaces
335 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_MECR_VAL 0x00000003
337#define CONFIG_SYS_MCMEM0_VAL 0x00014405
338#define CONFIG_SYS_MCMEM1_VAL 0x00014405
339#define CONFIG_SYS_MCATT0_VAL 0x00014405
340#define CONFIG_SYS_MCATT1_VAL 0x00014405
341#define CONFIG_SYS_MCIO0_VAL 0x00014405
342#define CONFIG_SYS_MCIO1_VAL 0x00014405
Wolfgang Denk70a20472005-09-25 15:59:01 +0200343
344/*
345 * FLASH and environment organization
346 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200348#define CONFIG_FLASH_CFI_DRIVER 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200349
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_MONITOR_BASE 0
351#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
Wolfgang Denk70a20472005-09-25 15:59:01 +0200352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
354#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200355
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200357
358/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
360#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
Wolfgang Denk70a20472005-09-25 15:59:01 +0200361
362/* put cfg at end of flash for now */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200363#define CONFIG_ENV_IS_IN_FLASH 1
Wolfgang Denk70a20472005-09-25 15:59:01 +0200364 /* Addr of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200365#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SIZE - 0x40000)
366#define CONFIG_ENV_SIZE PHYS_FLASH_SECT_SIZE /* Total Size of Environment Sector */
367#define CONFIG_ENV_SECT_SIZE (PHYS_FLASH_SECT_SIZE / 16)
Wolfgang Denk70a20472005-09-25 15:59:01 +0200368
369#endif /* __CONFIG_H */