Gitiles
Code Review Sign In
gerrit.cesnet.cz / github / trini / u-boot / adcdeacc3eda1e5949e54062aa99c299e12483be / . / board / freescale / t208xrdb / tlb.c
blob: 085d9f5c6a9c591e0327b4798b40dddd475a5928 [file] [log] [blame]
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800[diff] [blame]1/*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <asm/mmu.h>
12
13struct fsl_e_tlb_entry tlb_table[] = {
14 /* TLB 0 - for temp stack in cache */
15 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
16 CONFIG_SYS_INIT_RAM_ADDR_PHYS,
17 MAS3_SX|MAS3_SW|MAS3_SR, 0,
18 0, 0, BOOKE_PAGESZ_4K, 0),
19 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
20 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
24 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
25 MAS3_SX|MAS3_SW|MAS3_SR, 0,
26 0, 0, BOOKE_PAGESZ_4K, 0),
27 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
28 CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
29 MAS3_SX|MAS3_SW|MAS3_SR, 0,
30 0, 0, BOOKE_PAGESZ_4K, 0),
31
32 /* TLB 1 */
33 /* *I*** - Covers boot page */
34#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
35 /*
36 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
37 * SRAM is at 0xfff00000, it covered the 0xfffff000.
38 */
39 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
40 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 0, 0, BOOKE_PAGESZ_1M, 1),
42#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
43 /*
44 * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
45 * space is at 0xfff00000, it covered the 0xfffff000.
46 */
47 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
48 CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
49 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
50 0, 0, BOOKE_PAGESZ_1M, 1),
51#else
52 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
53 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
54 0, 0, BOOKE_PAGESZ_4K, 1),
55#endif
56
57 /* *I*G* - CCSRBAR */
58 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
59 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
60 0, 1, BOOKE_PAGESZ_16M, 1),
61
62 /* *I*G* - Flash, localbus */
63 /* This will be changed to *I*G* after relocation to RAM. */
64 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
65 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
66 0, 2, BOOKE_PAGESZ_256M, 1),
67
68 /* *I*G* - PCIe 1, 0x80000000 */
69 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
70 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71 0, 3, BOOKE_PAGESZ_512M, 1),
72
73 /* *I*G* - PCIe 2, 0xa0000000 */
74 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE2_MEM_VIRT, CONFIG_SYS_PCIE2_MEM_PHYS,
75 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
76 0, 4, BOOKE_PAGESZ_256M, 1),
77
78 /* *I*G* - PCIe 3, 0xb0000000 */
79 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
80 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
81 0, 5, BOOKE_PAGESZ_256M, 1),
82
83
84 /* *I*G* - PCIe 4, 0xc0000000 */
85 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE4_MEM_VIRT, CONFIG_SYS_PCIE4_MEM_PHYS,
86 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
87 0, 6, BOOKE_PAGESZ_256M, 1),
88
89 /* *I*G* - PCI I/O */
90 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
91 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
92 0, 7, BOOKE_PAGESZ_256K, 1),
93
94 /* Bman/Qman */
95#ifdef CONFIG_SYS_BMAN_MEM_PHYS
96 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
97 MAS3_SX|MAS3_SW|MAS3_SR, 0,
98 0, 9, BOOKE_PAGESZ_16M, 1),
99 SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
100 CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
101 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
102 0, 10, BOOKE_PAGESZ_16M, 1),
103#endif
104#ifdef CONFIG_SYS_QMAN_MEM_PHYS
105 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
106 MAS3_SX|MAS3_SW|MAS3_SR, 0,
107 0, 11, BOOKE_PAGESZ_16M, 1),
108 SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
109 CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
110 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
111 0, 12, BOOKE_PAGESZ_16M, 1),
112#endif
113#ifdef CONFIG_SYS_DCSRBAR_PHYS
114 SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
115 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
116 0, 13, BOOKE_PAGESZ_32M, 1),
117#endif
118#ifdef CONFIG_SYS_NAND_BASE
119 /*
120 * *I*G - NAND
121 * entry 14 and 15 has been used hard coded, they will be disabled
122 * in cpu_init_f, so we use entry 16 for nand.
123 */
124 SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
125 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
126 0, 16, BOOKE_PAGESZ_64K, 1),
127#endif
128#ifdef CONFIG_SYS_CPLD_BASE
129 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
130 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
131 0, 17, BOOKE_PAGESZ_4K, 1),
132#endif
133#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
134 /*
135 * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
136 * fetching ucode and ENV from master
137 */
138 SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
139 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
140 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
141 0, 18, BOOKE_PAGESZ_1M, 1),
142#endif
143#if defined(CONFIG_SYS_RAMBOOT)
144 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
145 MAS3_SX|MAS3_SW|MAS3_SR, 0,
146 0, 19, BOOKE_PAGESZ_2G, 1)
147#endif
148
149};
150
151int num_tlb_entries = ARRAY_SIZE(tlb_table);