| wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 1 | #ifndef _IMX_REGS_H |
| 2 | #define _IMX_REGS_H |
| 3 | /* ------------------------------------------------------------------------ |
| 4 | * Motorola IMX system registers |
| 5 | * ------------------------------------------------------------------------ |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | # ifndef __ASSEMBLY__ |
| 10 | # define __REG(x) (*((volatile u32 *)(x))) |
| 11 | # define __REG2(x,y) \ |
| 12 | ( __builtin_constant_p(y) ? (__REG((x) + (y))) \ |
| 13 | : (*(volatile u32 *)((u32)&__REG(x) + (y))) ) |
| 14 | # else |
| 15 | # define __REG(x) (x) |
| 16 | # define __REG2(x,y) ((x)+(y)) |
| 17 | #endif |
| 18 | |
| 19 | #define IMX_IO_BASE 0x00200000 |
| 20 | |
| 21 | /* |
| 22 | * Register BASEs, based on OFFSETs |
| 23 | * |
| 24 | */ |
| 25 | #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE) |
| 26 | #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE) |
| 27 | #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE) |
| 28 | #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE) |
| 29 | #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE) |
| 30 | #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE) |
| 31 | #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE) |
| 32 | #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE) |
| 33 | #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE) |
| 34 | #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE) |
| 35 | #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE) |
| 36 | #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE) |
| 37 | #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE) |
| 38 | #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE) |
| 39 | #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE) |
| 40 | #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE) |
| 41 | #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE) |
| 42 | #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE) |
| 43 | #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE) |
| 44 | #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE) |
| 45 | #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE) |
| 46 | #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE) |
| 47 | #define IMX_SYSCTRL_BASE (0x1B800 + IMX_IO_BASE) |
| 48 | #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE) |
| 49 | #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE) |
| 50 | #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE) |
| 51 | #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE) |
| 52 | #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE) |
| 53 | #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE) |
| 54 | |
| wdenk | b304c96 | 2005-04-05 22:30:50 +0000 | [diff] [blame] | 55 | /* Watchdog Registers*/ |
| 56 | |
| 57 | #define WCR __REG(IMX_WDT_BASE + 0x00) /* Watchdog Control Register */ |
| 58 | #define WSR __REG(IMX_WDT_BASE + 0x04) /* Watchdog Service Register */ |
| 59 | #define WSTR __REG(IMX_WDT_BASE + 0x08) /* Watchdog Status Register */ |
| 60 | |
| wdenk | 281e00a | 2004-08-01 22:48:16 +0000 | [diff] [blame] | 61 | /* SYSCTRL Registers */ |
| 62 | #define SIDR __REG(IMX_SYSCTRL_BASE + 0x4) /* Silicon ID Register */ |
| 63 | #define FMCR __REG(IMX_SYSCTRL_BASE + 0x8) /* Function Multiplex Control Register */ |
| 64 | #define GPCR __REG(IMX_SYSCTRL_BASE + 0xC) /* Function Multiplex Control Register */ |
| 65 | |
| 66 | /* Chip Select Registers */ |
| 67 | #define CS0U __REG(IMX_EIM_BASE) /* Chip Select 0 Upper Register */ |
| 68 | #define CS0L __REG(IMX_EIM_BASE + 0x4) /* Chip Select 0 Lower Register */ |
| 69 | #define CS1U __REG(IMX_EIM_BASE + 0x8) /* Chip Select 1 Upper Register */ |
| 70 | #define CS1L __REG(IMX_EIM_BASE + 0xc) /* Chip Select 1 Lower Register */ |
| 71 | #define CS2U __REG(IMX_EIM_BASE + 0x10) /* Chip Select 2 Upper Register */ |
| 72 | #define CS2L __REG(IMX_EIM_BASE + 0x14) /* Chip Select 2 Lower Register */ |
| 73 | #define CS3U __REG(IMX_EIM_BASE + 0x18) /* Chip Select 3 Upper Register */ |
| 74 | #define CS3L __REG(IMX_EIM_BASE + 0x1c) /* Chip Select 3 Lower Register */ |
| 75 | #define CS4U __REG(IMX_EIM_BASE + 0x20) /* Chip Select 4 Upper Register */ |
| 76 | #define CS4L __REG(IMX_EIM_BASE + 0x24) /* Chip Select 4 Lower Register */ |
| 77 | #define CS5U __REG(IMX_EIM_BASE + 0x28) /* Chip Select 5 Upper Register */ |
| 78 | #define CS5L __REG(IMX_EIM_BASE + 0x2c) /* Chip Select 5 Lower Register */ |
| 79 | #define EIM __REG(IMX_EIM_BASE + 0x30) /* EIM Configuration Register */ |
| 80 | |
| 81 | /* SDRAM controller registers */ |
| 82 | |
| 83 | #define SDCTL0 __REG(IMX_SDRAMC_BASE) /* SDRAM 0 Control Register */ |
| 84 | #define SDCTL1 __REG(IMX_SDRAMC_BASE + 0x4) /* SDRAM 1 Control Register */ |
| 85 | #define SDMISC __REG(IMX_SDRAMC_BASE + 0x14) /* Miscellaneous Register */ |
| 86 | #define SDRST __REG(IMX_SDRAMC_BASE + 0x18) /* SDRAM Reset Register */ |
| 87 | |
| 88 | /* PLL registers */ |
| 89 | #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ |
| 90 | #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ |
| 91 | #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ |
| 92 | #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */ |
| 93 | #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ |
| 94 | #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ |
| 95 | |
| 96 | #define CSCR_MPLL_RESTART (1<<21) |
| 97 | |
| 98 | /* |
| 99 | * GPIO Module and I/O Multiplexer |
| 100 | * x = 0..3 for reg_A, reg_B, reg_C, reg_D |
| 101 | */ |
| 102 | #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8) |
| 103 | #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8) |
| 104 | #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8) |
| 105 | #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8) |
| 106 | #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8) |
| 107 | #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8) |
| 108 | #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8) |
| 109 | #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8) |
| 110 | #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8) |
| 111 | #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8) |
| 112 | #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8) |
| 113 | #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8) |
| 114 | #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8) |
| 115 | #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8) |
| 116 | #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8) |
| 117 | #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8) |
| 118 | #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8) |
| 119 | |
| 120 | #define GPIO_PIN_MASK 0x1f |
| 121 | #define GPIO_PORT_MASK (0x3 << 5) |
| 122 | |
| 123 | #define GPIO_PORTA (0<<5) |
| 124 | #define GPIO_PORTB (1<<5) |
| 125 | #define GPIO_PORTC (2<<5) |
| 126 | #define GPIO_PORTD (3<<5) |
| 127 | |
| 128 | #define GPIO_OUT (1<<7) |
| 129 | #define GPIO_IN (0<<7) |
| 130 | #define GPIO_PUEN (1<<8) |
| 131 | |
| 132 | #define GPIO_PF (0<<9) |
| 133 | #define GPIO_AF (1<<9) |
| 134 | |
| 135 | #define GPIO_OCR_MASK (3<<10) |
| 136 | #define GPIO_AIN (0<<10) |
| 137 | #define GPIO_BIN (1<<10) |
| 138 | #define GPIO_CIN (2<<10) |
| 139 | #define GPIO_GPIO (3<<10) |
| 140 | |
| 141 | #define GPIO_AOUT (1<<12) |
| 142 | #define GPIO_BOUT (1<<13) |
| 143 | |
| 144 | /* assignements for GPIO alternate/primary functions */ |
| 145 | |
| 146 | /* FIXME: This list is not completed. The correct directions are |
| 147 | * missing on some (many) pins |
| 148 | */ |
| 149 | #define PA0_PF_A24 ( GPIO_PORTA | GPIO_PF | 0 ) |
| 150 | #define PA0_AIN_SPI2_CLK ( GPIO_PORTA | GPIO_OUT | GPIO_AIN | 0 ) |
| 151 | #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 ) |
| 152 | #define PA1_AOUT_SPI2_RXD ( GPIO_PORTA | GPIO_IN | GPIO_AOUT | 1 ) |
| 153 | #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 ) |
| 154 | #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 ) |
| 155 | #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 ) |
| 156 | #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 ) |
| 157 | #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 ) |
| 158 | #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 ) |
| 159 | #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 ) |
| 160 | #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 ) |
| 161 | #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 ) |
| 162 | #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 ) |
| 163 | #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 ) |
| 164 | #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 ) |
| 165 | #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 ) |
| 166 | #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 ) |
| 167 | #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 ) |
| 168 | #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 ) |
| 169 | #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 ) |
| 170 | #define PA17_AIN_SPI2_SS ( GPIO_PORTA | GPIO_AIN | 17 ) |
| 171 | #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 ) |
| 172 | #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 ) |
| 173 | #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 ) |
| 174 | #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 ) |
| 175 | #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 ) |
| 176 | #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 ) |
| 177 | #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 ) |
| 178 | #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 ) |
| 179 | #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 ) |
| 180 | #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 ) |
| 181 | #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 ) |
| 182 | #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 ) |
| 183 | #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 ) |
| 184 | #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 ) |
| 185 | #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 ) |
| 186 | #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 ) |
| 187 | #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 ) |
| 188 | #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 ) |
| 189 | #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 ) |
| 190 | #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 ) |
| 191 | #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 ) |
| 192 | #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 ) |
| 193 | #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 ) |
| 194 | #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 ) |
| 195 | #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 ) |
| 196 | #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 ) |
| 197 | #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 ) |
| 198 | #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 ) |
| 199 | #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 11 ) |
| 200 | #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 ) |
| 201 | #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | GPIO_OUT | 12 ) |
| 202 | #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 ) |
| 203 | #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_OUT | GPIO_PUEN | 13 ) |
| 204 | #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 ) |
| 205 | #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 ) |
| 206 | #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 ) |
| 207 | #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 ) |
| 208 | #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 ) |
| 209 | #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 ) |
| 210 | #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 ) |
| 211 | #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 ) |
| 212 | #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 ) |
| 213 | #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 ) |
| 214 | #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 ) |
| 215 | #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 ) |
| 216 | #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 ) |
| 217 | #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 ) |
| 218 | #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 ) |
| 219 | #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 ) |
| 220 | #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 ) |
| 221 | #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 ) |
| 222 | #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 ) |
| 223 | #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 ) |
| 224 | #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 ) |
| 225 | #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 ) |
| 226 | #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 ) |
| 227 | #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 ) |
| 228 | #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 ) |
| 229 | #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 ) |
| 230 | #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 ) |
| 231 | #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 ) |
| 232 | #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 ) |
| 233 | #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 ) |
| 234 | #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 ) |
| 235 | #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 ) |
| 236 | #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 ) |
| 237 | #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 ) |
| 238 | #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 ) |
| 239 | #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 ) |
| 240 | #define PD7_AF_UART2_DTR ( GPIO_PORTD | GPIO_IN | GPIO_AF | 7 ) |
| 241 | #define PD7_AIN_SPI2_SCLK ( GPIO_PORTD | GPIO_AIN | 7 ) |
| 242 | #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 ) |
| 243 | #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 ) |
| 244 | #define PD8_AIN_SPI2_SS ( GPIO_PORTD | GPIO_AIN | 8 ) |
| 245 | #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 ) |
| 246 | #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 ) |
| 247 | #define PD9_AOUT_SPI2_RXD ( GPIO_PORTD | GPIO_IN | GPIO_AOUT | 9 ) |
| 248 | #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 ) |
| 249 | #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 ) |
| 250 | #define PD10_AIN_SPI2_TXD ( GPIO_PORTD | GPIO_OUT | GPIO_AIN | 10 ) |
| 251 | #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 ) |
| 252 | #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 ) |
| 253 | #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 ) |
| 254 | #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 ) |
| 255 | #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 ) |
| 256 | #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 ) |
| 257 | #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 ) |
| 258 | #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 ) |
| 259 | #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 ) |
| 260 | #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 ) |
| 261 | #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 ) |
| 262 | #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 ) |
| 263 | #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 ) |
| 264 | #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 ) |
| 265 | #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 ) |
| 266 | #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 ) |
| 267 | #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 ) |
| 268 | #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 ) |
| 269 | #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 ) |
| 270 | #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 ) |
| 271 | #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 ) |
| 272 | #define PD31_BIN_SPI2_TXD ( GPIO_PORTD | GPIO_BIN | 31 ) |
| 273 | |
| 274 | /* |
| 275 | * DMA Controller |
| 276 | */ |
| 277 | #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */ |
| 278 | #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */ |
| 279 | #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */ |
| 280 | #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */ |
| 281 | #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */ |
| 282 | #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */ |
| 283 | #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */ |
| 284 | #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */ |
| 285 | #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */ |
| 286 | #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */ |
| 287 | #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */ |
| 288 | #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */ |
| 289 | #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */ |
| 290 | #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */ |
| 291 | #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */ |
| 292 | #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */ |
| 293 | #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */ |
| 294 | #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /*Â Control Registers */ |
| 295 | #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */ |
| 296 | #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */ |
| 297 | #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */ |
| 298 | #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */ |
| 299 | |
| 300 | /* TODO: define DMA_REQ lines */ |
| 301 | |
| 302 | #define DCR_DRST (1<<1) |
| 303 | #define DCR_DEN (1<<0) |
| 304 | #define DBTOCR_EN (1<<15) |
| 305 | #define DBTOCR_CNT(x) ((x) & 0x7fff ) |
| 306 | #define CNTR_CNT(x) ((x) & 0xffffff ) |
| 307 | #define CCR_DMOD_LINEAR ( 0x0 << 12 ) |
| 308 | #define CCR_DMOD_2D ( 0x1 << 12 ) |
| 309 | #define CCR_DMOD_FIFO ( 0x2 << 12 ) |
| 310 | #define CCR_DMOD_EOBFIFO ( 0x3 << 12 ) |
| 311 | #define CCR_SMOD_LINEAR ( 0x0 << 10 ) |
| 312 | #define CCR_SMOD_2D ( 0x1 << 10 ) |
| 313 | #define CCR_SMOD_FIFO ( 0x2 << 10 ) |
| 314 | #define CCR_SMOD_EOBFIFO ( 0x3 << 10 ) |
| 315 | #define CCR_MDIR_DEC (1<<9) |
| 316 | #define CCR_MSEL_B (1<<8) |
| 317 | #define CCR_DSIZ_32 ( 0x0 << 6 ) |
| 318 | #define CCR_DSIZ_8 ( 0x1 << 6 ) |
| 319 | #define CCR_DSIZ_16 ( 0x2 << 6 ) |
| 320 | #define CCR_SSIZ_32 ( 0x0 << 4 ) |
| 321 | #define CCR_SSIZ_8 ( 0x1 << 4 ) |
| 322 | #define CCR_SSIZ_16 ( 0x2 << 4 ) |
| 323 | #define CCR_REN (1<<3) |
| 324 | #define CCR_RPT (1<<2) |
| 325 | #define CCR_FRC (1<<1) |
| 326 | #define CCR_CEN (1<<0) |
| 327 | #define RTOR_EN (1<<15) |
| 328 | #define RTOR_CLK (1<<14) |
| 329 | #define RTOR_PSC (1<<13) |
| 330 | |
| 331 | /* |
| 332 | * LCD Controller |
| 333 | */ |
| 334 | |
| 335 | #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00) |
| 336 | |
| 337 | #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04) |
| 338 | #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20) |
| 339 | #define SIZE_YMAX(y) ( (y) & 0x1ff ) |
| 340 | |
| 341 | #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08) |
| 342 | #define VPW_VPW(x) ( (x) & 0x3ff ) |
| 343 | |
| 344 | #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C) |
| 345 | #define CPOS_CC1 (1<<31) |
| 346 | #define CPOS_CC0 (1<<30) |
| 347 | #define CPOS_OP (1<<28) |
| 348 | #define CPOS_CXP(x) (((x) & 3ff) << 16) |
| 349 | #define CPOS_CYP(y) ((y) & 0x1ff) |
| 350 | |
| 351 | #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10) |
| 352 | #define LCWHB_BK_EN (1<<31) |
| 353 | #define LCWHB_CW(w) (((w) & 0x1f) << 24) |
| 354 | #define LCWHB_CH(h) (((h) & 0x1f) << 16) |
| 355 | #define LCWHB_BD(x) ((x) & 0xff) |
| 356 | |
| 357 | #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14) |
| 358 | #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11) |
| 359 | #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5) |
| 360 | #define LCHCC_CUR_COL_B(b) ((b) & 0x1f) |
| 361 | |
| 362 | #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18) |
| 363 | #define PCR_TFT (1<<31) |
| 364 | #define PCR_COLOR (1<<30) |
| 365 | #define PCR_PBSIZ_1 (0<<28) |
| 366 | #define PCR_PBSIZ_2 (1<<28) |
| 367 | #define PCR_PBSIZ_4 (2<<28) |
| 368 | #define PCR_PBSIZ_8 (3<<28) |
| 369 | #define PCR_BPIX_1 (0<<25) |
| 370 | #define PCR_BPIX_2 (1<<25) |
| 371 | #define PCR_BPIX_4 (2<<25) |
| 372 | #define PCR_BPIX_8 (3<<25) |
| 373 | #define PCR_BPIX_12 (4<<25) |
| 374 | #define PCR_BPIX_16 (4<<25) |
| 375 | #define PCR_PIXPOL (1<<24) |
| 376 | #define PCR_FLMPOL (1<<23) |
| 377 | #define PCR_LPPOL (1<<22) |
| 378 | #define PCR_CLKPOL (1<<21) |
| 379 | #define PCR_OEPOL (1<<20) |
| 380 | #define PCR_SCLKIDLE (1<<19) |
| 381 | #define PCR_END_SEL (1<<18) |
| 382 | #define PCR_END_BYTE_SWAP (1<<17) |
| 383 | #define PCR_REV_VS (1<<16) |
| 384 | #define PCR_ACD_SEL (1<<15) |
| 385 | #define PCR_ACD(x) (((x) & 0x7f) << 8) |
| 386 | #define PCR_SCLK_SEL (1<<7) |
| 387 | #define PCR_SHARP (1<<6) |
| 388 | #define PCR_PCD(x) ((x) & 0x3f) |
| 389 | |
| 390 | #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C) |
| 391 | #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26) |
| 392 | #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8) |
| 393 | #define HCR_H_WAIT_2(x) ((x) & 0xff) |
| 394 | |
| 395 | #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20) |
| 396 | #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26) |
| 397 | #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8) |
| 398 | #define VCR_V_WAIT_2(x) ((x) & 0xff) |
| 399 | |
| 400 | #define LCDC_POS __REG(IMX_LCDC_BASE+0x24) |
| 401 | #define POS_POS(x) ((x) & 1f) |
| 402 | |
| 403 | #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28) |
| 404 | #define LSCR1_GRAY1(x) (((x) & 0xf) << 4) |
| 405 | #define LSCR1_GRAY2(x) ((x) & 0xf) |
| 406 | |
| 407 | #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C) |
| 408 | #define PWMR_CLS(x) (((x) & 0x1ff) << 16) |
| 409 | #define PWMR_LDMSK (1<<15) |
| 410 | #define PWMR_SCR1 (1<<10) |
| 411 | #define PWMR_SCR0 (1<<9) |
| 412 | #define PWMR_CC_EN (1<<8) |
| 413 | #define PWMR_PW(x) ((x) & 0xff) |
| 414 | |
| 415 | #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30) |
| 416 | #define DMACR_BURST (1<<31) |
| 417 | #define DMACR_HM(x) (((x) & 0xf) << 16) |
| 418 | #define DMACR_TM(x) ((x) &0xf) |
| 419 | |
| 420 | #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34) |
| 421 | #define RMCR_LCDC_EN (1<<1) |
| 422 | #define RMCR_SELF_REF (1<<0) |
| 423 | |
| 424 | #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38) |
| 425 | #define LCDICR_INT_SYN (1<<2) |
| 426 | #define LCDICR_INT_CON (1) |
| 427 | |
| 428 | #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40) |
| 429 | #define LCDISR_UDR_ERR (1<<3) |
| 430 | #define LCDISR_ERR_RES (1<<2) |
| 431 | #define LCDISR_EOF (1<<1) |
| 432 | #define LCDISR_BOF (1<<0) |
| 433 | /* |
| 434 | * UART Module |
| 435 | */ |
| 436 | #define URXD0(x) __REG2( IMX_UART1_BASE + 0x0, ((x) & 1) << 12) /* Receiver Register */ |
| 437 | #define URTX0(x) __REG2( IMX_UART1_BASE + 0x40, ((x) & 1) << 12) /* Transmitter Register */ |
| 438 | #define UCR1(x) __REG2( IMX_UART1_BASE + 0x80, ((x) & 1) << 12) /* Control Register 1 */ |
| 439 | #define UCR2(x) __REG2( IMX_UART1_BASE + 0x84, ((x) & 1) << 12) /* Control Register 2 */ |
| 440 | #define UCR3(x) __REG2( IMX_UART1_BASE + 0x88, ((x) & 1) << 12) /* Control Register 3 */ |
| 441 | #define UCR4(x) __REG2( IMX_UART1_BASE + 0x8c, ((x) & 1) << 12) /* Control Register 4 */ |
| 442 | #define UFCR(x) __REG2( IMX_UART1_BASE + 0x90, ((x) & 1) << 12) /* FIFO Control Register */ |
| 443 | #define USR1(x) __REG2( IMX_UART1_BASE + 0x94, ((x) & 1) << 12) /* Status Register 1 */ |
| 444 | #define USR2(x) __REG2( IMX_UART1_BASE + 0x98, ((x) & 1) << 12) /* Status Register 2 */ |
| 445 | #define UESC(x) __REG2( IMX_UART1_BASE + 0x9c, ((x) & 1) << 12) /* Escape Character Register */ |
| 446 | #define UTIM(x) __REG2( IMX_UART1_BASE + 0xa0, ((x) & 1) << 12) /* Escape Timer Register */ |
| 447 | #define UBIR(x) __REG2( IMX_UART1_BASE + 0xa4, ((x) & 1) << 12) /* BRM Incremental Register */ |
| 448 | #define UBMR(x) __REG2( IMX_UART1_BASE + 0xa8, ((x) & 1) << 12) /* BRM Modulator Register */ |
| 449 | #define UBRC(x) __REG2( IMX_UART1_BASE + 0xac, ((x) & 1) << 12) /* Baud Rate Count Register */ |
| 450 | #define BIPR1(x) __REG2( IMX_UART1_BASE + 0xb0, ((x) & 1) << 12) /* Incremental Preset Register 1 */ |
| 451 | #define BIPR2(x) __REG2( IMX_UART1_BASE + 0xb4, ((x) & 1) << 12) /* Incremental Preset Register 2 */ |
| 452 | #define BIPR3(x) __REG2( IMX_UART1_BASE + 0xb8, ((x) & 1) << 12) /* Incremental Preset Register 3 */ |
| 453 | #define BIPR4(x) __REG2( IMX_UART1_BASE + 0xbc, ((x) & 1) << 12) /* Incremental Preset Register 4 */ |
| 454 | #define BMPR1(x) __REG2( IMX_UART1_BASE + 0xc0, ((x) & 1) << 12) /* BRM Modulator Register 1 */ |
| 455 | #define BMPR2(x) __REG2( IMX_UART1_BASE + 0xc4, ((x) & 1) << 12) /* BRM Modulator Register 2 */ |
| 456 | #define BMPR3(x) __REG2( IMX_UART1_BASE + 0xc8, ((x) & 1) << 12) /* BRM Modulator Register 3 */ |
| 457 | #define BMPR4(x) __REG2( IMX_UART1_BASE + 0xcc, ((x) & 1) << 12) /* BRM Modulator Register 4 */ |
| 458 | #define UTS(x) __REG2( IMX_UART1_BASE + 0xd0, ((x) & 1) << 12) /* UART Test Register */ |
| 459 | |
| 460 | /* UART Control Register Bit Fields.*/ |
| 461 | #define URXD_CHARRDY (1<<15) |
| 462 | #define URXD_ERR (1<<14) |
| 463 | #define URXD_OVRRUN (1<<13) |
| 464 | #define URXD_FRMERR (1<<12) |
| 465 | #define URXD_BRK (1<<11) |
| 466 | #define URXD_PRERR (1<<10) |
| 467 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ |
| 468 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ |
| 469 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ |
| 470 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ |
| 471 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ |
| 472 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ |
| 473 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ |
| 474 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ |
| 475 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ |
| 476 | #define UCR1_SNDBRK (1<<4) /* Send break */ |
| 477 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ |
| 478 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ |
| 479 | #define UCR1_DOZE (1<<1) /* Doze */ |
| 480 | #define UCR1_UARTEN (1<<0) /* UART enabled */ |
| 481 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ |
| 482 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ |
| 483 | #define UCR2_CTSC (1<<13) /* CTS pin control */ |
| 484 | #define UCR2_CTS (1<<12) /* Clear to send */ |
| 485 | #define UCR2_ESCEN (1<<11) /* Escape enable */ |
| 486 | #define UCR2_PREN (1<<8) /* Parity enable */ |
| 487 | #define UCR2_PROE (1<<7) /* Parity odd/even */ |
| 488 | #define UCR2_STPB (1<<6) /* Stop */ |
| 489 | #define UCR2_WS (1<<5) /* Word size */ |
| 490 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ |
| 491 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ |
| 492 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ |
| 493 | #define UCR2_SRST (1<<0) /* SW reset */ |
| 494 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ |
| 495 | #define UCR3_PARERREN (1<<12) /* Parity enable */ |
| 496 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ |
| 497 | #define UCR3_DSR (1<<10) /* Data set ready */ |
| 498 | #define UCR3_DCD (1<<9) /* Data carrier detect */ |
| 499 | #define UCR3_RI (1<<8) /* Ring indicator */ |
| 500 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ |
| 501 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ |
| 502 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ |
| 503 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ |
| 504 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ |
| 505 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ |
| 506 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ |
| 507 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ |
| 508 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ |
| 509 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ |
| 510 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ |
| 511 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ |
| 512 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ |
| 513 | #define UCR4_IRSC (1<<5) /* IR special case */ |
| 514 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ |
| 515 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ |
| 516 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ |
| 517 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ |
| 518 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ |
| 519 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ |
| 520 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ |
| 521 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ |
| 522 | #define USR1_RTSS (1<<14) /* RTS pin status */ |
| 523 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ |
| 524 | #define USR1_RTSD (1<<12) /* RTS delta */ |
| 525 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ |
| 526 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ |
| 527 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ |
| 528 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ |
| 529 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ |
| 530 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ |
| 531 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ |
| 532 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ |
| 533 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ |
| 534 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ |
| 535 | #define USR2_IDLE (1<<12) /* Idle condition */ |
| 536 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ |
| 537 | #define USR2_WAKE (1<<7) /* Wake */ |
| 538 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ |
| 539 | #define USR2_TXDC (1<<3) /* Transmitter complete */ |
| 540 | #define USR2_BRCD (1<<2) /* Break condition */ |
| 541 | #define USR2_ORE (1<<1) /* Overrun error */ |
| 542 | #define USR2_RDR (1<<0) /* Recv data ready */ |
| 543 | #define UTS_FRCPERR (1<<13) /* Force parity error */ |
| 544 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ |
| 545 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ |
| 546 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ |
| 547 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ |
| 548 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ |
| 549 | #define UTS_SOFTRST (1<<0) /* Software reset */ |
| 550 | |
| 551 | /* General purpose timers registers */ |
| 552 | #define TCTL1 __REG(IMX_TIM1_BASE) |
| 553 | #define TPRER1 __REG(IMX_TIM1_BASE + 0x4) |
| 554 | #define TCMP1 __REG(IMX_TIM1_BASE + 0x8) |
| 555 | #define TCR1 __REG(IMX_TIM1_BASE + 0xc) |
| 556 | #define TCN1 __REG(IMX_TIM1_BASE + 0x10) |
| 557 | #define TSTAT1 __REG(IMX_TIM1_BASE + 0x14) |
| 558 | #define TCTL2 __REG(IMX_TIM2_BASE) |
| 559 | #define TPRER2 __REG(IMX_TIM2_BASE + 0x4) |
| 560 | #define TCMP2 __REG(IMX_TIM2_BASE + 0x8) |
| 561 | #define TCR2 __REG(IMX_TIM2_BASE + 0xc) |
| 562 | #define TCN2 __REG(IMX_TIM2_BASE + 0x10) |
| 563 | #define TSTAT2 __REG(IMX_TIM2_BASE + 0x14) |
| 564 | |
| 565 | /* General purpose timers bitfields */ |
| 566 | #define TCTL_SWR (1<<15) /* Software reset */ |
| 567 | #define TCTL_FRR (1<<8) /* Freerun / restart */ |
| 568 | #define TCTL_CAP (3<<6) /* Capture Edge */ |
| 569 | #define TCTL_OM (1<<5) /* output mode */ |
| 570 | #define TCTL_IRQEN (1<<4) /* interrupt enable */ |
| 571 | #define TCTL_CLKSOURCE (7<<1) /* Clock source */ |
| 572 | #define TCTL_TEN (1) /* Timer enable */ |
| 573 | #define TPRER_PRES (0xff) /* Prescale */ |
| 574 | #define TSTAT_CAPT (1<<1) /* Capture event */ |
| 575 | #define TSTAT_COMP (1) /* Compare event */ |
| 576 | |
| 577 | #endif /* _IMX_REGS_H */ |