blob: a7cee5138db2a4a51ee26d47c420a8751ad051e7 [file] [log] [blame]
Alessandro Rubini0d8c6ea2009-02-09 15:53:31 +01001/*
2 * (C) Copyright 2007 STMicroelectronics, <www.st.com>
3 * (C) Copyright 2009 Alessandro Rubini <rubini@unipv.it>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Alessandro Rubini0d8c6ea2009-02-09 15:53:31 +01006 */
7
8#include <common.h>
9#include <nand.h>
10#include <asm/io.h>
11
12static inline int parity(int b) /* b is really a byte; returns 0 or ~0 */
13{
14 __asm__ __volatile__(
15 "eor %0, %0, %0, lsr #4\n\t"
16 "eor %0, %0, %0, lsr #2\n\t"
17 "eor %0, %0, %0, lsr #1\n\t"
18 "ands %0, %0, #1\n\t"
19 "subne %0, %0, #2\t"
20 : "=r" (b) : "0" (b));
21 return b;
22}
23
24/*
25 * This is the ECC routine used in hardware, according to the manual.
26 * HW claims to make the calculation but not the correction; so we must
27 * recalculate the bytes for a comparison.
28 */
Jean-Christophe PLAGNIOL-VILLARD0176c032009-02-22 17:56:50 +010029static int ecc512(const unsigned char *data, unsigned char *ecc)
Alessandro Rubini0d8c6ea2009-02-09 15:53:31 +010030{
31 int gpar = 0;
32 int i, val, par;
33 int pbits = 0; /* P8, P16, ... P2048 */
34 int pprime = 0; /* P8', P16', ... P2048' */
35 int lowbits; /* P1, P2, P4 and primes */
36
37 for (i = 0; i < 512; i++) {
38 par = parity((val = data[i]));
39 gpar ^= val;
40 pbits ^= (i & par);
41 }
42 /*
43 * Ok, now gpar is global parity (xor of all bytes)
44 * pbits are all the parity bits (non-prime ones)
45 */
46 par = parity(gpar);
47 pprime = pbits ^ par;
48 /* Put low bits in the right position for ecc[2] (bits 7..2) */
49 lowbits = 0
50 | (parity(gpar & 0xf0) & 0x80) /* P4 */
51 | (parity(gpar & 0x0f) & 0x40) /* P4' */
52 | (parity(gpar & 0xcc) & 0x20) /* P2 */
53 | (parity(gpar & 0x33) & 0x10) /* P2' */
54 | (parity(gpar & 0xaa) & 0x08) /* P1 */
55 | (parity(gpar & 0x55) & 0x04); /* P1' */
56
57 ecc[2] = ~(lowbits | ((pbits & 0x100) >> 7) | ((pprime & 0x100) >> 8));
58 /* now intermix bits for ecc[1] (P1024..P128') and ecc[0] (P64..P8') */
59 ecc[1] = ~( (pbits & 0x80) >> 0 | ((pprime & 0x80) >> 1)
60 | ((pbits & 0x40) >> 1) | ((pprime & 0x40) >> 2)
61 | ((pbits & 0x20) >> 2) | ((pprime & 0x20) >> 3)
62 | ((pbits & 0x10) >> 3) | ((pprime & 0x10) >> 4));
63
64 ecc[0] = ~( (pbits & 0x8) << 4 | ((pprime & 0x8) << 3)
65 | ((pbits & 0x4) << 3) | ((pprime & 0x4) << 2)
66 | ((pbits & 0x2) << 2) | ((pprime & 0x2) << 1)
67 | ((pbits & 0x1) << 1) | ((pprime & 0x1) << 0));
68 return 0;
69}
70
71/* This is the method in the chip->ecc field */
72static int nomadik_ecc_calculate(struct mtd_info *mtd, const uint8_t *dat,
73 uint8_t *ecc_code)
74{
75 return ecc512(dat, ecc_code);
76}
77
78static int nomadik_ecc_correct(struct mtd_info *mtd, uint8_t *dat,
79 uint8_t *r_ecc, uint8_t *c_ecc)
80{
81 struct nand_chip *chip = mtd->priv;
82 uint32_t r, c, d, diff; /*read, calculated, xor of them */
83
84 if (!memcmp(r_ecc, c_ecc, chip->ecc.bytes))
85 return 0;
86
87 /* Reorder the bytes into ascending-order 24 bits -- see manual */
88 r = r_ecc[2] << 22 | r_ecc[1] << 14 | r_ecc[0] << 6 | r_ecc[2] >> 2;
89 c = c_ecc[2] << 22 | c_ecc[1] << 14 | c_ecc[0] << 6 | c_ecc[2] >> 2;
90 diff = (r ^ c) & ((1<<24)-1); /* use 24 bits only */
91
92 /* If 12 bits are different, one per pair, it's correctable */
93 if (((diff | (diff>>1)) & 0x555555) == 0x555555) {
94 int bit = ((diff & 2) >> 1)
95 | ((diff & 0x8) >> 2) | ((diff & 0x20) >> 3);
96 int byte;
97
98 d = diff >> 6; /* remove bit-order info */
99 byte = ((d & 2) >> 1)
100 | ((d & 0x8) >> 2) | ((d & 0x20) >> 3)
101 | ((d & 0x80) >> 4) | ((d & 0x200) >> 5)
102 | ((d & 0x800) >> 6) | ((d & 0x2000) >> 7)
103 | ((d & 0x8000) >> 8) | ((d & 0x20000) >> 9);
104 /* correct the single bit */
105 dat[byte] ^= 1<<bit;
106 return 0;
107 }
108 /* If 1 bit only differs, it's one bit error in ECC, ignore */
109 if ((diff ^ (1 << (ffs(diff) - 1))) == 0)
110 return 0;
111 /* Otherwise, uncorrectable */
112 return -1;
113}
114
115static void nomadik_ecc_hwctl(struct mtd_info *mtd, int mode)
116{ /* mandatory in the structure but not used here */ }
117
118
119/* This is the layout used by older installations, we keep compatible */
120struct nand_ecclayout nomadik_ecc_layout = {
121 .eccbytes = 3 * 4,
122 .eccpos = { /* each subpage has 16 bytes: pos 2,3,4 hosts ECC */
123 0x02, 0x03, 0x04,
124 0x12, 0x13, 0x14,
125 0x22, 0x23, 0x24,
126 0x32, 0x33, 0x34},
127 .oobfree = { {0x08, 0x08}, {0x18, 0x08}, {0x28, 0x08}, {0x38, 0x08} },
128};
129
130#define MASK_ALE (1 << 24) /* our ALE is AD21 */
131#define MASK_CLE (1 << 23) /* our CLE is AD22 */
132
133/* This is copied from the AT91SAM9 devices (Stelian Pop, Lead Tech Design) */
134static void nomadik_nand_hwcontrol(struct mtd_info *mtd,
135 int cmd, unsigned int ctrl)
136{
137 struct nand_chip *this = mtd->priv;
138 u32 pcr0 = readl(REG_FSMC_PCR0);
139
140 if (ctrl & NAND_CTRL_CHANGE) {
141 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
142 IO_ADDR_W &= ~(MASK_ALE | MASK_CLE);
143
144 if (ctrl & NAND_CLE)
145 IO_ADDR_W |= MASK_CLE;
146 if (ctrl & NAND_ALE)
147 IO_ADDR_W |= MASK_ALE;
148
149 if (ctrl & NAND_NCE)
150 writel(pcr0 | 0x4, REG_FSMC_PCR0);
151 else
152 writel(pcr0 & ~0x4, REG_FSMC_PCR0);
153
154 this->IO_ADDR_W = (void *) IO_ADDR_W;
155 this->IO_ADDR_R = (void *) IO_ADDR_W;
156 }
157
158 if (cmd != NAND_CMD_NONE)
159 writeb(cmd, this->IO_ADDR_W);
160}
161
162/* Returns 1 when ready; upper layers timeout at 20ms with timer routines */
163static int nomadik_nand_ready(struct mtd_info *mtd)
164{
165 return 1; /* The ready bit is handled in hardware */
166}
167
168/* Copy a buffer 32bits at a time: faster than defualt method which is 8bit */
169static void nomadik_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
170{
171 int i;
172 struct nand_chip *chip = mtd->priv;
173 u32 *p = (u32 *) buf;
174
175 len >>= 2;
176 writel(0, REG_FSMC_ECCR0);
177 for (i = 0; i < len; i++)
178 p[i] = readl(chip->IO_ADDR_R);
179}
180
181int board_nand_init(struct nand_chip *chip)
182{
183 /* Set up the FSMC_PCR0 for nand access*/
184 writel(0x0000004a, REG_FSMC_PCR0);
185 /* Set up FSMC_PMEM0, FSMC_PATT0 with timing data for access */
186 writel(0x00020401, REG_FSMC_PMEM0);
187 writel(0x00020404, REG_FSMC_PATT0);
188
189 chip->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING;
190 chip->cmd_ctrl = nomadik_nand_hwcontrol;
191 chip->dev_ready = nomadik_nand_ready;
192 /* The chip allows 32bit reads, so avoid the default 8bit copy */
193 chip->read_buf = nomadik_nand_read_buf;
194
195 /* ECC: follow the hardware-defined rulse, but do it in sw */
196 chip->ecc.mode = NAND_ECC_HW;
197 chip->ecc.bytes = 3;
198 chip->ecc.size = 512;
Sergey Lapindfe64e22013-01-14 03:46:50 +0000199 chip->ecc.strength = 1;
Alessandro Rubini0d8c6ea2009-02-09 15:53:31 +0100200 chip->ecc.layout = &nomadik_ecc_layout;
201 chip->ecc.calculate = nomadik_ecc_calculate;
202 chip->ecc.hwctl = nomadik_ecc_hwctl;
203 chip->ecc.correct = nomadik_ecc_correct;
204
205 return 0;
206}