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Stelian Pop8e429b32008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Stelian Pop56a24792008-05-08 14:52:31 +020026#include <asm/sizes.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020027#include <asm/arch/at91sam9263.h>
28#include <asm/arch/at91sam9263_matrix.h>
29#include <asm/arch/at91sam9_smc.h>
30#include <asm/arch/at91_pmc.h>
31#include <asm/arch/at91_rstc.h>
32#include <asm/arch/gpio.h>
33#include <asm/arch/io.h>
Ben Warren3ae071e2008-08-12 22:11:53 -070034#include <asm/arch/hardware.h>
Stelian Pop56a24792008-05-08 14:52:31 +020035#include <lcd.h>
36#include <atmel_lcdc.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020037#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
38#include <net.h>
39#endif
Ben Warren3ae071e2008-08-12 22:11:53 -070040#include <netdev.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020041
42DECLARE_GLOBAL_DATA_PTR;
43
44/* ------------------------------------------------------------------------- */
45/*
46 * Miscelaneous platform dependent initialisations
47 */
48
49static void at91sam9263ek_serial_hw_init(void)
50{
51#ifdef CONFIG_USART0
52 at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
53 at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
Stelian Popc91e17a2008-11-07 12:09:21 +010054 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
Stelian Pop8e429b32008-05-08 18:52:23 +020055#endif
56
57#ifdef CONFIG_USART1
58 at91_set_A_periph(AT91_PIN_PD0, 1); /* TXD1 */
59 at91_set_A_periph(AT91_PIN_PD1, 0); /* RXD1 */
Stelian Popc91e17a2008-11-07 12:09:21 +010060 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US1);
Stelian Pop8e429b32008-05-08 18:52:23 +020061#endif
62
63#ifdef CONFIG_USART2
64 at91_set_A_periph(AT91_PIN_PD2, 1); /* TXD2 */
65 at91_set_A_periph(AT91_PIN_PD3, 0); /* RXD2 */
Stelian Popc91e17a2008-11-07 12:09:21 +010066 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US2);
Stelian Pop8e429b32008-05-08 18:52:23 +020067#endif
68
69#ifdef CONFIG_USART3 /* DBGU */
70 at91_set_A_periph(AT91_PIN_PC30, 0); /* DRXD */
71 at91_set_A_periph(AT91_PIN_PC31, 1); /* DTXD */
72 at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
73#endif
74}
75
76#ifdef CONFIG_CMD_NAND
77static void at91sam9263ek_nand_hw_init(void)
78{
79 unsigned long csa;
80
81 /* Enable CS3 */
82 csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
83 at91_sys_write(AT91_MATRIX_EBI0CSA,
84 csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
85
86 /* Configure SMC CS3 for NAND/SmartMedia */
87 at91_sys_write(AT91_SMC_SETUP(3),
Patrice Vilchezd3bcdf82008-05-27 11:15:29 +020088 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
89 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
Stelian Pop8e429b32008-05-08 18:52:23 +020090 at91_sys_write(AT91_SMC_PULSE(3),
91 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
92 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
93 at91_sys_write(AT91_SMC_CYCLE(3),
94 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
95 at91_sys_write(AT91_SMC_MODE(3),
96 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
97 AT91_SMC_EXNWMODE_DISABLE |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#ifdef CONFIG_SYS_NAND_DBW_16
Stelian Pop8e429b32008-05-08 18:52:23 +020099 AT91_SMC_DBW_16 |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#else /* CONFIG_SYS_NAND_DBW_8 */
Stelian Pop8e429b32008-05-08 18:52:23 +0200101 AT91_SMC_DBW_8 |
102#endif
103 AT91_SMC_TDF_(2));
104
105 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA |
106 1 << AT91SAM9263_ID_PIOCDE);
107
108 /* Configure RDY/BSY */
109 at91_set_gpio_input(AT91_PIN_PA22, 1);
110
111 /* Enable NandFlash */
112 at91_set_gpio_output(AT91_PIN_PD15, 1);
113}
114#endif
115
116#ifdef CONFIG_HAS_DATAFLASH
117static void at91sam9263ek_spi_hw_init(void)
118{
119 at91_set_B_periph(AT91_PIN_PA5, 0); /* SPI0_NPCS0 */
120
121 at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
122 at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
123 at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */
124
125 /* Enable clock */
126 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_SPI0);
127}
128#endif
129
130#ifdef CONFIG_MACB
131static void at91sam9263ek_macb_hw_init(void)
132{
133 /* Enable clock */
134 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
135
136 /*
137 * Disable pull-up on:
138 * RXDV (PC25) => PHY normal mode (not Test mode)
139 * ERX0 (PE25) => PHY ADDR0
140 * ERX1 (PE26) => PHY ADDR1 => PHYADDR = 0x0
141 *
142 * PHY has internal pull-down
143 */
144 writel(pin_to_mask(AT91_PIN_PC25),
145 pin_to_controller(AT91_PIN_PC0) + PIO_PUDR);
146 writel(pin_to_mask(AT91_PIN_PE25) |
147 pin_to_mask(AT91_PIN_PE26),
148 pin_to_controller(AT91_PIN_PE0) + PIO_PUDR);
149
150 /* Need to reset PHY -> 500ms reset */
151 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
Stelian Pop19bd6882008-05-22 00:15:40 +0200152 (AT91_RSTC_ERSTL & (0x0D << 8)) |
Stelian Pop8e429b32008-05-08 18:52:23 +0200153 AT91_RSTC_URSTEN);
154
155 at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
156
157 /* Wait for end hardware reset */
158 while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
159
Stelian Pop19bd6882008-05-22 00:15:40 +0200160 /* Restore NRST value */
161 at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
162 (AT91_RSTC_ERSTL & (0x0 << 8)) |
163 AT91_RSTC_URSTEN);
164
Stelian Pop8e429b32008-05-08 18:52:23 +0200165 /* Re-enable pull-up */
166 writel(pin_to_mask(AT91_PIN_PC25),
167 pin_to_controller(AT91_PIN_PC0) + PIO_PUER);
168 writel(pin_to_mask(AT91_PIN_PE25) |
169 pin_to_mask(AT91_PIN_PE26),
170 pin_to_controller(AT91_PIN_PE0) + PIO_PUER);
171
172 at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */
173 at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */
174 at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */
175 at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */
176 at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */
177 at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */
178 at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */
179 at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */
180 at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */
181 at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */
182
183#ifndef CONFIG_RMII
184 at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */
185 at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */
186 at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */
187 at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */
188 at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */
189 at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */
190 at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */
191 at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */
192#endif
193
194}
195#endif
196
197#ifdef CONFIG_USB_OHCI_NEW
198static void at91sam9263ek_uhp_hw_init(void)
199{
200 /* Enable VBus on UHP ports */
201 at91_set_gpio_output(AT91_PIN_PA21, 0);
202 at91_set_gpio_output(AT91_PIN_PA24, 0);
203}
204#endif
205
Stelian Pop56a24792008-05-08 14:52:31 +0200206#ifdef CONFIG_LCD
207vidinfo_t panel_info = {
208 vl_col: 240,
209 vl_row: 320,
210 vl_clk: 4965000,
211 vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
212 ATMEL_LCDC_INVFRAME_INVERTED,
213 vl_bpix: 3,
214 vl_tft: 1,
215 vl_hsync_len: 5,
216 vl_left_margin: 1,
217 vl_right_margin:33,
218 vl_vsync_len: 1,
219 vl_upper_margin:1,
220 vl_lower_margin:0,
221 mmio: AT91SAM9263_LCDC_BASE,
222};
223
224void lcd_enable(void)
225{
226 at91_set_gpio_value(AT91_PIN_PA30, 1); /* power up */
227}
228
229void lcd_disable(void)
230{
231 at91_set_gpio_value(AT91_PIN_PA30, 0); /* power down */
232}
233
234static void at91sam9263ek_lcd_hw_init(void)
235{
236 at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
237 at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
238 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
239 at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
240 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
241 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
242 at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
243 at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
244 at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
245 at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
246 at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
247 at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
248 at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
249 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
250 at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
251 at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
252 at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
253 at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
254 at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
255 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
256 at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
257 at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
258
259 at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
260
261 gd->fb_base = AT91SAM9263_SRAM0_BASE;
262}
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200263
264#ifdef CONFIG_LCD_INFO
265#include <nand.h>
266#include <version.h>
267
268void lcd_show_board_info(void)
269{
270 ulong dram_size, nand_size;
271 int i;
272 char temp[32];
273
274 lcd_printf ("%s\n", U_BOOT_VERSION);
275 lcd_printf ("(C) 2008 ATMEL Corp\n");
276 lcd_printf ("at91support@atmel.com\n");
277 lcd_printf ("%s CPU at %s MHz\n",
278 AT91_CPU_NAME,
Stelian Popad229a42008-11-07 13:55:14 +0100279 strmhz(temp, AT91_CPU_CLOCK));
Haavard Skinnemoen6b59e032008-09-01 16:21:22 +0200280
281 dram_size = 0;
282 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
283 dram_size += gd->bd->bi_dram[i].size;
284 nand_size = 0;
285 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
286 nand_size += nand_info[i].size;
287 lcd_printf (" %ld MB SDRAM, %ld MB NAND\n",
288 dram_size >> 20,
289 nand_size >> 20 );
290}
291#endif /* CONFIG_LCD_INFO */
Stelian Pop56a24792008-05-08 14:52:31 +0200292#endif
293
Stelian Pop8e429b32008-05-08 18:52:23 +0200294int board_init(void)
295{
296 /* Enable Ctrlc */
297 console_init_f();
298
299 /* arch number of AT91SAM9263EK-Board */
300 gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9263EK;
301 /* adress of boot parameters */
302 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
303
304 at91sam9263ek_serial_hw_init();
305#ifdef CONFIG_CMD_NAND
306 at91sam9263ek_nand_hw_init();
307#endif
308#ifdef CONFIG_HAS_DATAFLASH
309 at91sam9263ek_spi_hw_init();
310#endif
311#ifdef CONFIG_MACB
312 at91sam9263ek_macb_hw_init();
313#endif
314#ifdef CONFIG_USB_OHCI_NEW
315 at91sam9263ek_uhp_hw_init();
316#endif
Stelian Pop56a24792008-05-08 14:52:31 +0200317#ifdef CONFIG_LCD
318 at91sam9263ek_lcd_hw_init();
319#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200320 return 0;
321}
322
323int dram_init(void)
324{
325 gd->bd->bi_dram[0].start = PHYS_SDRAM;
326 gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
327 return 0;
328}
329
330#ifdef CONFIG_RESET_PHY_R
331void reset_phy(void)
332{
333#ifdef CONFIG_MACB
334 /*
335 * Initialize ethernet HW addr prior to starting Linux,
336 * needed for nfsroot
337 */
338 eth_init(gd->bd);
339#endif
340}
341#endif
Ben Warren3ae071e2008-08-12 22:11:53 -0700342
343int board_eth_init(bd_t *bis)
344{
345 int rc = 0;
346#ifdef CONFIG_MACB
Stelian Popd8003fa2008-11-07 13:54:31 +0100347 rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
Ben Warren3ae071e2008-08-12 22:11:53 -0700348#endif
349 return rc;
350}