blob: ab23f5c209d61091f5fe1da65b6722a552f4919a [file] [log] [blame]
Nicolas Ferre44b5c402019-08-08 07:48:26 +00001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * at91-sama5d27_wlsom1_ek.dts - Device Tree file for SAMA5D27 WLSOM1 EK
4 *
5 * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
6 *
7 * Author: Nicolas Ferre <nicolas.ferre@microcihp.com>
8 */
9/dts-v1/;
10#include "sama5d27_wlsom1.dtsi"
11
12/ {
13 model = "Microchip SAMA5D27 WLSOM1 EK";
14 compatible = "microchip,sama5d27-wlsom1-ek", "microchip,sama5d27-wlsom1", "atmel,sama5d2", "atmel,sama5";
15
16 chosen {
17 stdout-path = &uart0;
18 };
19
20 onewire_tm: onewire {
21 gpios = <&pioA PIN_PC9 0>;
22 pinctrl-names = "default";
23 pinctrl-0 = <&pinctrl_onewire_tm_default>;
24 status = "okay";
25
26 w1_eeprom: w1_eeprom@0 {
27 compatible = "maxim,ds24b33";
28 status = "okay";
29 };
30 };
31
32 ahb {
33 sdmmc0: sdio-host@a0000000 {
34 bus-width = <4>;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
37 status = "okay";
38 };
39
40 apb {
Eugen Hristev4a500e42019-08-26 11:45:06 +000041 hlcdc: hlcdc@f0000000 {
42 atmel,vl-bpix = <4>;
43 atmel,output-mode = <24>;
44 atmel,guard-time = <1>;
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_lcd_base &pinctrl_lcd_pwm &pinctrl_lcd_rgb666>;
47 status = "okay";
48
49 display-timings {
50 800x480 {
51 clock-frequency = <33300000>;
52 xres = <800>;
53 yres = <480>;
54 hactive = <800>;
55 vactive = <480>;
56 hsync-len = <64>;
57 hfront-porch = <1>;
58 hback-porch = <64>;
59 vfront-porch = <1>;
60 vback-porch = <22>;
61 vsync-len = <23>;
62 };
63 };
64 };
65
Eugen Hristev06e0da72019-08-26 06:47:06 +000066 qspi1: spi@f0024000 {
67 status = "okay";
68 };
69
Nicolas Ferre44b5c402019-08-08 07:48:26 +000070 macb0: ethernet@f8008000 {
71 status = "okay";
72 };
73
74 uart0: serial@f801c000 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_uart0_default>;
77 status = "okay";
78 };
79
80 pioA: gpio@fc038000 {
81 pinctrl {
Eugen Hristev4a500e42019-08-26 11:45:06 +000082 pinctrl_lcd_base: pinctrl_lcd_base {
83 pinmux = <PIN_PC30__LCDVSYNC>,
84 <PIN_PC31__LCDHSYNC>,
85 <PIN_PD1__LCDDEN>,
86 <PIN_PD0__LCDPCK>;
87 bias-disable;
88 };
89
90 pinctrl_lcd_pwm: pinctrl_lcd_pwm {
91 pinmux = <PIN_PC28__LCDPWM>;
92 bias-disable;
93 };
94
95 pinctrl_lcd_rgb666: pinctrl_lcd_rgb666 {
96 pinmux = <PIN_PC10__LCDDAT2>,
97 <PIN_PC11__LCDDAT3>,
98 <PIN_PC12__LCDDAT4>,
99 <PIN_PC13__LCDDAT5>,
100 <PIN_PC14__LCDDAT6>,
101 <PIN_PC15__LCDDAT7>,
102 <PIN_PC16__LCDDAT10>,
103 <PIN_PC17__LCDDAT11>,
104 <PIN_PC18__LCDDAT12>,
105 <PIN_PC19__LCDDAT13>,
106 <PIN_PC20__LCDDAT14>,
107 <PIN_PC21__LCDDAT15>,
108 <PIN_PC22__LCDDAT18>,
109 <PIN_PC23__LCDDAT19>,
110 <PIN_PC24__LCDDAT20>,
111 <PIN_PC25__LCDDAT21>,
112 <PIN_PC26__LCDDAT22>,
113 <PIN_PC27__LCDDAT23>;
114 bias-disable;
115 };
116
Nicolas Ferre44b5c402019-08-08 07:48:26 +0000117 pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
118 pinmux = <PIN_PA1__SDMMC0_CMD>,
119 <PIN_PA2__SDMMC0_DAT0>,
120 <PIN_PA3__SDMMC0_DAT1>,
121 <PIN_PA4__SDMMC0_DAT2>,
122 <PIN_PA5__SDMMC0_DAT3>;
123 bias-disable;
124 };
125
126 pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
127 pinmux = <PIN_PA0__SDMMC0_CK>,
128 <PIN_PA11__SDMMC0_VDDSEL>,
129 <PIN_PA12__SDMMC0_WP>,
130 <PIN_PA13__SDMMC0_CD>;
131 bias-disable;
132 };
133
134 pinctrl_uart0_default: uart0_default {
135 pinmux = <PIN_PB26__URXD0>,
136 <PIN_PB27__UTXD0>;
137 bias-disable;
138 };
139
140 pinctrl_onewire_tm_default: onewire_tm_default {
141 pinmux = <PIN_PC9__GPIO>;
142 bias-pull-up;
143 };
144 };
145 };
146 };
147 };
148};