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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simekdea4d2f2017-11-02 10:54:48 +01002/*
3 * (C) Copyright 2013 - 2017 Xilinx.
4 *
5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
Michal Simekdea4d2f2017-11-02 10:54:48 +01007 */
8
9#ifndef __CONFIG_ZYNQ_CSE_H
10#define __CONFIG_ZYNQ_CSE_H
11
12#define CONFIG_SKIP_LOWLEVEL_INIT
Michal Simekdea4d2f2017-11-02 10:54:48 +010013
14#include <configs/zynq-common.h>
15
16/* Undef unneeded configs */
17#undef CONFIG_EXTRA_ENV_SETTINGS
Michal Simekdea4d2f2017-11-02 10:54:48 +010018
Michal Simekdea4d2f2017-11-02 10:54:48 +010019#undef CONFIG_SYS_CBSIZE
Michal Simekdea4d2f2017-11-02 10:54:48 +010020
21#define CONFIG_SYS_CBSIZE 1024
22
Michal Simekdea4d2f2017-11-02 10:54:48 +010023#undef CONFIG_SYS_INIT_RAM_ADDR
24#undef CONFIG_SYS_INIT_RAM_SIZE
25#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
26#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
27#undef CONFIG_SPL_BSS_START_ADDR
28#undef CONFIG_SPL_BSS_MAX_SIZE
29#define CONFIG_SPL_BSS_START_ADDR 0x20000
30#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
31
Michal Simekdea4d2f2017-11-02 10:54:48 +010032#endif /* __CONFIG_ZYNQ_CSE_H */