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Kumar Gala58e5e9a2008-08-26 15:01:29 -05001/*
York Sun34e026f2014-03-27 17:54:47 -07002 * Copyright 2008-2014 Freescale Semiconductor, Inc.
Kumar Gala58e5e9a2008-08-26 15:01:29 -05003 *
Tom Riniac727572018-02-14 21:34:05 -05004 * SPDX-License-Identifier: GPL-2.0
Kumar Gala58e5e9a2008-08-26 15:01:29 -05005 */
6
7#ifndef FSL_DDR_MAIN_H
8#define FSL_DDR_MAIN_H
9
York Sun34e026f2014-03-27 17:54:47 -070010#include <fsl_ddrc_version.h>
York Sun5614e712013-09-30 09:22:09 -070011#include <fsl_ddr_sdram.h>
12#include <fsl_ddr_dimm_params.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050013
York Sun5614e712013-09-30 09:22:09 -070014#include <common_timing_params.h>
Kumar Gala58e5e9a2008-08-26 15:01:29 -050015
York Sun1d71efb2014-08-01 15:51:00 -070016#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS
17/* All controllers are for main memory */
York Sun51370d52016-12-28 08:43:45 -080018#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_SYS_NUM_DDR_CTLRS
York Sun1d71efb2014-08-01 15:51:00 -070019#endif
20
York Sun4e5b1bd2014-02-10 13:59:42 -080021#ifdef CONFIG_SYS_FSL_DDR_LE
22#define ddr_in32(a) in_le32(a)
23#define ddr_out32(a, v) out_le32(a, v)
York Sundda3b612014-12-08 15:30:55 -080024#define ddr_setbits32(a, v) setbits_le32(a, v)
25#define ddr_clrbits32(a, v) clrbits_le32(a, v)
26#define ddr_clrsetbits32(a, clear, set) clrsetbits_le32(a, clear, set)
York Sun4e5b1bd2014-02-10 13:59:42 -080027#else
28#define ddr_in32(a) in_be32(a)
29#define ddr_out32(a, v) out_be32(a, v)
York Sundda3b612014-12-08 15:30:55 -080030#define ddr_setbits32(a, v) setbits_be32(a, v)
31#define ddr_clrbits32(a, v) clrbits_be32(a, v)
32#define ddr_clrsetbits32(a, clear, set) clrsetbits_be32(a, clear, set)
York Sun4e5b1bd2014-02-10 13:59:42 -080033#endif
34
York Sun66869f92015-03-19 09:30:26 -070035u32 fsl_ddr_get_version(unsigned int ctrl_num);
York Sun34e026f2014-03-27 17:54:47 -070036
York Sun1b3e3c42011-06-07 09:42:16 +080037#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
Kumar Gala58e5e9a2008-08-26 15:01:29 -050038/*
39 * Bind the main DDR setup driver's generic names
40 * to this specific DDR technology.
41 */
42static __inline__ int
York Sun03e664d2015-01-06 13:18:50 -080043compute_dimm_parameters(const unsigned int ctrl_num,
44 const generic_spd_eeprom_t *spd,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050045 dimm_params_t *pdimm,
46 unsigned int dimm_number)
47{
York Sun03e664d2015-01-06 13:18:50 -080048 return ddr_compute_dimm_parameters(ctrl_num, spd, pdimm, dimm_number);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050049}
York Sun1b3e3c42011-06-07 09:42:16 +080050#endif
Kumar Gala58e5e9a2008-08-26 15:01:29 -050051
52/*
53 * Data Structures
54 *
55 * All data structures have to be on the stack
56 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR
Kumar Gala58e5e9a2008-08-26 15:01:29 -050058
59typedef struct {
60 generic_spd_eeprom_t
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061 spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
Kumar Gala58e5e9a2008-08-26 15:01:29 -050062 struct dimm_params_s
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR];
64 memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS];
65 common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS];
66 fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS];
York Sun1d71efb2014-08-01 15:51:00 -070067 unsigned int first_ctrl;
68 unsigned int num_ctrls;
69 unsigned long long mem_base;
70 unsigned int dimm_slots_per_ctrl;
71 int (*board_need_mem_reset)(void);
72 void (*board_mem_reset)(void);
73 void (*board_mem_de_reset)(void);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050074} fsl_ddr_info_t;
75
76/* Compute steps */
77#define STEP_GET_SPD (1 << 0)
78#define STEP_COMPUTE_DIMM_PARMS (1 << 1)
79#define STEP_COMPUTE_COMMON_PARMS (1 << 2)
80#define STEP_GATHER_OPTS (1 << 3)
81#define STEP_ASSIGN_ADDRESSES (1 << 4)
82#define STEP_COMPUTE_REGS (1 << 5)
83#define STEP_PROGRAM_REGS (1 << 6)
84#define STEP_ALL 0xFFF
85
York Sun6f5e1dc2011-09-16 13:21:35 -070086unsigned long long
Haiying Wangfc0c2b62010-12-01 10:35:31 -050087fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
88 unsigned int size_only);
York Sun6f5e1dc2011-09-16 13:21:35 -070089const char *step_to_string(unsigned int step);
Kumar Gala58e5e9a2008-08-26 15:01:29 -050090
York Sun03e664d2015-01-06 13:18:50 -080091unsigned int compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
92 const memctl_options_t *popts,
Kumar Gala58e5e9a2008-08-26 15:01:29 -050093 fsl_ddr_cfg_regs_t *ddr,
94 const common_timing_params_t *common_dimm,
95 const dimm_params_t *dimm_parameters,
Haiying Wangfc0c2b62010-12-01 10:35:31 -050096 unsigned int dbw_capacity_adjust,
97 unsigned int size_only);
York Sun6f5e1dc2011-09-16 13:21:35 -070098unsigned int compute_lowest_common_dimm_parameters(
York Sun03e664d2015-01-06 13:18:50 -080099 const unsigned int ctrl_num,
York Sun6f5e1dc2011-09-16 13:21:35 -0700100 const dimm_params_t *dimm_params,
101 common_timing_params_t *outpdimm,
102 unsigned int number_of_dimms);
York Sun56848422015-07-23 14:04:48 -0700103unsigned int populate_memctl_options(const common_timing_params_t *common_dimm,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500104 memctl_options_t *popts,
Haiying Wangdfb49102008-10-03 12:36:55 -0400105 dimm_params_t *pdimm,
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500106 unsigned int ctrl_num);
York Sun6f5e1dc2011-09-16 13:21:35 -0700107void check_interleaving_options(fsl_ddr_info_t *pinfo);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500108
York Sun03e664d2015-01-06 13:18:50 -0800109unsigned int mclk_to_picos(const unsigned int ctrl_num, unsigned int mclk);
110unsigned int get_memory_clk_period_ps(const unsigned int ctrl_num);
111unsigned int picos_to_mclk(const unsigned int ctrl_num, unsigned int picos);
York Sun6f5e1dc2011-09-16 13:21:35 -0700112void fsl_ddr_set_lawbar(
113 const common_timing_params_t *memctl_common_params,
114 unsigned int memctl_interleaved,
115 unsigned int ctrl_num);
York Sune32d59a2015-01-06 13:18:55 -0800116void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl,
117 unsigned int last_ctrl);
York Sun6f5e1dc2011-09-16 13:21:35 -0700118
James Yange8ba6c52013-01-07 14:01:03 +0000119int fsl_ddr_interactive_env_var_exists(void);
120unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set);
York Sun6f5e1dc2011-09-16 13:21:35 -0700121void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
York Sun1d71efb2014-08-01 15:51:00 -0700122 unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl);
York Sun6f5e1dc2011-09-16 13:21:35 -0700123
124int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
125unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr);
York Sun4e5b1bd2014-02-10 13:59:42 -0800126void board_add_ram_info(int use_default);
York Sun6f5e1dc2011-09-16 13:21:35 -0700127
128/* processor specific function */
129void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
York Sunc63e1372013-06-25 11:37:48 -0700130 unsigned int ctrl_num, int step);
York Sun61bd2f72015-11-04 09:53:10 -0800131void remove_unused_controllers(fsl_ddr_info_t *info);
York Sun1b3e3c42011-06-07 09:42:16 +0800132
133/* board specific function */
134int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
135 unsigned int controller_number,
136 unsigned int dimm_number);
York Sunb92557c2015-05-28 14:54:08 +0530137void update_spd_address(unsigned int ctrl_num,
138 unsigned int slot,
139 unsigned int *addr);
Shengzhou Liu02fb2762016-11-21 11:36:48 +0800140
141void erratum_a009942_check_cpo(void);
Kumar Gala58e5e9a2008-08-26 15:01:29 -0500142#endif