wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2002 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* for now: just dummy functions to satisfy the linker */ |
| 9 | |
wdenk | 8ed9604 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 10 | #include <common.h> |
| 11 | |
Jeroen Hofstee | fcfddfd | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 12 | __weak void flush_cache(unsigned long start, unsigned long size) |
wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 13 | { |
Tom Rini | 7f5eef9 | 2013-06-04 12:02:06 +0000 | [diff] [blame] | 14 | #if defined(CONFIG_ARM1136) |
wdenk | 8ed9604 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 15 | |
Albert ARIBAUD | b4ee149 | 2014-04-15 16:13:47 +0200 | [diff] [blame] | 16 | #if !defined(CONFIG_SYS_ICACHE_OFF) |
| 17 | asm("mcr p15, 0, r1, c7, c5, 0"); /* invalidate I cache */ |
wdenk | 8ed9604 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 18 | #endif |
Albert ARIBAUD | b4ee149 | 2014-04-15 16:13:47 +0200 | [diff] [blame] | 19 | |
| 20 | #if !defined(CONFIG_SYS_DCACHE_OFF) |
| 21 | asm("mcr p15, 0, r1, c7, c14, 0"); /* Clean+invalidate D cache */ |
| 22 | #endif |
| 23 | |
| 24 | #endif /* CONFIG_ARM1136 */ |
| 25 | |
Heiko Schocher | c3330e9 | 2010-09-17 13:10:30 +0200 | [diff] [blame] | 26 | #ifdef CONFIG_ARM926EJS |
| 27 | /* test and clean, page 2-23 of arm926ejs manual */ |
| 28 | asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); |
| 29 | /* disable write buffer as well (page 2-22) */ |
| 30 | asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); |
Albert ARIBAUD | b4ee149 | 2014-04-15 16:13:47 +0200 | [diff] [blame] | 31 | #endif /* CONFIG_ARM926EJS */ |
wdenk | edc48b6 | 2002-09-08 17:56:50 +0000 | [diff] [blame] | 32 | return; |
| 33 | } |
Aneesh V | e05f007 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 34 | |
| 35 | /* |
| 36 | * Default implementation: |
| 37 | * do a range flush for the entire range |
| 38 | */ |
Jeroen Hofstee | fcfddfd | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 39 | __weak void flush_dcache_all(void) |
Aneesh V | e05f007 | 2011-06-16 23:30:50 +0000 | [diff] [blame] | 40 | { |
| 41 | flush_cache(0, ~0); |
| 42 | } |
Aneesh V | cba4b18 | 2011-08-16 04:33:05 +0000 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * Default implementation of enable_caches() |
| 46 | * Real implementation should be in platform code |
| 47 | */ |
Jeroen Hofstee | fcfddfd | 2014-06-23 22:07:04 +0200 | [diff] [blame] | 48 | __weak void enable_caches(void) |
Aneesh V | cba4b18 | 2011-08-16 04:33:05 +0000 | [diff] [blame] | 49 | { |
| 50 | puts("WARNING: Caches not enabled\n"); |
| 51 | } |