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Eric Millbrandt5b53b292009-08-13 10:14:21 -05001/*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2006
6 * Eric Schumann, Phytec Messatechnik GmbH
7 *
8 * (C) Copyright 2009
9 * Jon Smirl <jonsmirl@gmail.com>
10 *
11 * (C) Copyright 2009
12 * Eric Millbrandt, DEKA Research and Development Corporation
13 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020014 * SPDX-License-Identifier: GPL-2.0+
Eric Millbrandt5b53b292009-08-13 10:14:21 -050015 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
20#define CONFIG_BOARDINFO "galaxy5200"
21
22/*
23 * High Level Configuration Options
24 * (easy to change)
25 */
26#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
27#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */
28#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
Eric Millbrandt5b53b292009-08-13 10:14:21 -050029
30/*
Wolfgang Denk2ae18242010-10-06 09:05:45 +020031 * Valid values for CONFIG_SYS_TEXT_BASE are:
32 * 0xFFF00000 boot high (standard configuration)
33 * 0xFE000000 boot low
34 * 0x00100000 boot from RAM (for testing only) does not work
35 */
36#ifdef CONFIG_galaxy5200_LOWBOOT
37#define CONFIG_SYS_TEXT_BASE 0xFE000000
38#endif
39
40#ifndef CONFIG_SYS_TEXT_BASE
41#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
42#endif
43
44/*
Eric Millbrandt5b53b292009-08-13 10:14:21 -050045 * Serial console configuration
46 */
47#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
48 /* define gps port conf. */
49 /* register later on to */
50 /* enable UART function! */
51#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
52#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
53
54/*
55 * Command line configuration.
56 */
57#include <config_cmd_default.h>
58
59#define CONFIG_CMD_DATE
60#define CONFIG_CMD_DHCP
61#define CONFIG_CMD_EEPROM
62#define CONFIG_CMD_I2C
63#define CONFIG_CMD_JFFS2
64#define CONFIG_CMD_MII
65#define CONFIG_CMD_NFS
66#define CONFIG_CMD_SNTP
67#define CONFIG_CMD_PING
68#define CONFIG_CMD_ASKENV
69#define CONFIG_CMD_USB
70#define CONFIG_CMD_CACHE
71#define CONFIG_CMD_FAT
72
73#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
74
Wolfgang Denk14d0a022010-10-07 21:51:12 +020075#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
Eric Millbrandt5b53b292009-08-13 10:14:21 -050076#define CONFIG_SYS_LOWBOOT 1
77#endif
78/* RAMBOOT will be defined automatically in memory section */
79
Eric Millbrandt0d042032009-08-25 10:30:26 -050080#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
81#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
Eric Millbrandt5b53b292009-08-13 10:14:21 -050082 "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
83
84/*
85 * Autobooting
86 */
Eric Millbrandt353462f2009-10-28 09:37:33 -050087#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
Eric Millbrandt5b53b292009-08-13 10:14:21 -050088#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
89 /* even with bootdelay=0 */
Eric Millbrandt353462f2009-10-28 09:37:33 -050090#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
91#define CONFIG_RESET_TO_RETRY
Eric Millbrandt5b53b292009-08-13 10:14:21 -050092
93#define CONFIG_PREBOOT "echo;" \
Eric Millbrandt0d042032009-08-25 10:30:26 -050094 "echo Welcome to U-Boot;"\
Eric Millbrandt5b53b292009-08-13 10:14:21 -050095 "echo"
96
Eric Millbrandt353462f2009-10-28 09:37:33 -050097#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
98 "bootm ff040000 ff900000 fffc0000"
99#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
100#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
101
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500102/*
103 * IPB Bus clocking configuration.
104 */
105#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
106#define CONFIG_SYS_XLB_PIPELINING 1
107
108/*
109 * I2C configuration
110 */
111#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
112#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
113#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
114#define CONFIG_SYS_I2C_SLAVE 0x7F
Eric Millbrandt5da71ef2009-09-03 08:09:44 -0500115#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500116
117/*
118 * EEPROM CAT24WC32 configuration
119 */
120#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
121#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
122#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
123#define CONFIG_SYS_EEPROM_SIZE 4096
124#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
125#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
126
127/*
128 * RTC configuration
129 */
130#define RTC
131#define CONFIG_RTC_DS3231 1
132#define CONFIG_SYS_I2C_RTC_ADDR 0x68
133
134/*
135 * Flash configuration
136 */
137
138#define CONFIG_SYS_FLASH_BASE 0xfe000000
139/*
Stefan Roesea47a12b2010-04-15 16:07:28 +0200140 * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500141 * variable defined
142 */
143#define CONFIG_SYS_FLASH_SIZE 0x02000000
144#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
145
146#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
147#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
148#define CONFIG_SYS_FLASH_EMPTY_INFO
149#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
150#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
151 /* (= chip selects) */
152#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
153
154/*
155 * Use hardware protection. This seems required, as the BDI uses hardware
156 * protection. Without this, U-Boot can't work with this sectors as its
157 * protection is software only by default.
158 */
159#define CONFIG_SYS_FLASH_PROTECTION 1
160
161/*
162 * Environment settings
163 */
164
165#define CONFIG_ENV_IS_IN_EEPROM 1
166#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
167 /* beginning of the EEPROM */
168#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
169
170#define CONFIG_ENV_OVERWRITE 1
171
172/*
173 * SDRAM configuration
174 */
175#define SDRAM_DDR 1
176#define SDRAM_MODE 0x018D0000
177#define SDRAM_EMODE 0x40090000
178#define SDRAM_CONTROL 0x71500F00
179#define SDRAM_CONFIG1 0x73711930
180#define SDRAM_CONFIG2 0x47770000
181
182/*
183 * Memory map
184 */
185#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
186 /* bootloader or debugger config */
187#define CONFIG_SYS_SDRAM_BASE 0x00000000
188#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
189
190/* Use SRAM until RAM will be available */
191#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
192
193/* End of used area in SPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200194#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500195
Wolfgang Denk553f0982010-10-26 13:32:32 +0200196#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200197 GENERATED_GBL_DATA_SIZE)
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
199
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200200#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500201#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
202# define CONFIG_SYS_RAMBOOT 1
203#endif
204
205#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
206#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
207#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
208
209/* Chip Select configuration for NAND flash */
210#define CONFIG_SYS_CS1_START 0x20000000
211#define CONFIG_SYS_CS1_SIZE 0x90000
Eric Millbrandt45def0a2009-09-25 17:47:43 -0500212#define CONFIG_SYS_CS1_CFG 0x00025b00
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500213
Eric Millbrandt795d2462009-08-28 07:14:04 -0500214/* Chip Select configuration for Epson S1D13513 */
215#define CONFIG_SYS_CS3_START 0x10000000
216#define CONFIG_SYS_CS3_SIZE 0x400000
217#define CONFIG_SYS_CS3_CFG 0xffff3d10
218
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500219/*
220 * Ethernet configuration
221 */
222#define CONFIG_MPC5xxx_FEC 1
223#define CONFIG_MPC5xxx_FEC_MII100
224#define CONFIG_PHY_ADDR 0x01
225#define CONFIG_NO_AUTOLOAD 1
226
227/*
228 * GPIO configuration
229 *
230 * GPS port configuration
231 *
232 * [29:31] = 01x
233 * AC97 on PSC1
234 * PSC1_0 -> AC97 SDATA out
235 * PSC1_1 -> AC97 SDTA in
236 * PSC1_2 -> AC97 SYNC out
237 * PSC1_3 -> AC97 bitclock out
238 * PSC1_4 -> AC97 reset out
239 *
240 * [28] = Reserved
241 *
242 * [25:27] = 110
243 * SPI on PSC2
244 * PSC2_0 -> MOSI
245 * PSC2_1 -> MISO
246 * PSC2_2 -> n/a
247 * PSC2_3 -> CLK
248 * PSC2_4 -> SS
249 *
250 * [24] = Reserved
251 *
252 * [20:23] = 0001
253 * USB on PSC3
254 * PSC3_0 -> USB_OE OE out
255 * PSC3_1 -> USB_TXN Tx- out
256 * PSC3_2 -> USB_TXP Tx+ out
257 * PSC3_3 -> USB_TXD
258 * PSC3_4 -> USB_RXP Rx+ in
259 * PSC3_5 -> USB_RXN Rx- in
260 * PSC3_6 -> USB_PWR PortPower out
261 * PSC3_7 -> USB_SPEED speed out
262 * PSC3_8 -> USB_SUSPEND suspend
263 * PSC3_9 -> USB_OVRCURNT overcurrent in
264 *
265 * [18:19] = 10
266 * Two UARTs
267 *
268 * [17] = 0
269 * USB differential mode
270 *
271 * [16] = 1
272 * PCI disabled
273 *
274 * [12:15] = 0101
275 * Ethernet 100Mbit with MD
276 * ETH_0 -> ETH Txen
277 * ETH_1 -> ETH TxD0
278 * ETH_2 -> ETH TxD1
279 * ETH_3 -> ETH TxD2
280 * ETH_4 -> ETH TxD3
281 * ETH_5 -> ETH Txerr
282 * ETH_6 -> ETH MDC
283 * ETH_7 -> ETH MDIO
284 * ETH_8 -> ETH RxDv
285 * ETH_9 -> ETH RxCLK
286 * ETH_10 -> ETH Collision
287 * ETH_11 -> ETH TxD
288 * ETH_12 -> ETH RxD0
289 * ETH_13 -> ETH RxD1
290 * ETH_14 -> ETH RxD2
291 * ETH_15 -> ETH RxD3
292 * ETH_16 -> ETH Rxerr
293 * ETH_17 -> ETH CRS
294 *
295 * [9:11] = 111
296 * SPI on PSC6
297 * PSC6_0 -> MISO
298 * PSC6_1 -> SS#
299 * PSC6_2 -> MOSI
300 * PSC6_3 -> CLK
301 *
302 * [8] = 0
303 * IrDA/USB 48MHz clock generated internally
304 *
305 * [6:7] = 01
306 * ATA chip selects on csb_4/5
307 * CSB_4 -> ATA_CS0 out
308 * CSB_5 -> ATA_CS1 out
309 *
310 * [5] = 1
311 * PSC3_4 is used as CS6
312 *
313 * [4] = 1
314 * PSC3_5 is used as CS7
315 *
316 * [2:3] = 00
317 * No Alternatives
318 *
319 * [1] = 0
320 * gpio_wkup_7 is GPIO
321 *
322 * [0] = 0
323 * gpio_wkup_6 is GPIO
324 *
325 */
326#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
327
328/*
329 * Miscellaneous configurable options
330 */
331#define CONFIG_SYS_LONGHELP /* undef to save memory */
332#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
333
334#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
335
336#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
337#if defined(CONFIG_CMD_KGDB)
338#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
339#endif
340
341#if defined(CONFIG_CMD_KGDB)
342#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
343#else
344#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
345#endif
346#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
347 /* Print Buffer Size */
348#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
349#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
350
351#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
352#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
353
354#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
355#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
356
357#define CONFIG_DISPLAY_BOARDINFO 1
358
359#define CONFIG_SYS_HUSH_PARSER 1
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500360
361#define CONFIG_CRC32_VERIFY 1
362
363#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
364 CONFIG_BOOTP_DNS | \
365 CONFIG_BOOTP_DNS2 | \
366 CONFIG_BOOTP_SEND_HOSTNAME )
367
Eric Millbrandt71ce9bd2009-09-21 11:05:55 -0500368#define CONFIG_VERSION_VARIABLE 1
369
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500370/*
371 * Various low-level settings
372 */
373#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
374#define CONFIG_SYS_HID0_FINAL HID0_ICE
375
376/* no burst access on the LPB */
377#define CONFIG_SYS_CS_BURST 0x00000000
378/* one deadcycle for the 33MHz statemachine */
379#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
380
381#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
382#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
383#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
384
Eric Millbrandt0d042032009-08-25 10:30:26 -0500385#define CONFIG_SYS_RESET_ADDRESS 0xff000000
Eric Millbrandt5b53b292009-08-13 10:14:21 -0500386
387/*
388 * USB settings
389 */
390#define CONFIG_USB_CLOCK 0x0001bbbb
391/* USB is on PSC3 */
392#define CONFIG_PSC3_USB
393#define CONFIG_USB_CONFIG 0x00000100
394#define CONFIG_USB_OHCI
395#define CONFIG_USB_STORAGE
396
397/*
398 * IDE/ATA stuff Supports IDE harddisk
399 */
400#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
401#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
402#undef CONFIG_IDE_LED /* LED for ide not supported */
403
404#define CONFIG_IDE_RESET 1 /* reset for ide supported */
405#define CONFIG_IDE_PREINIT
406#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
407#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
408#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
409#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
410/* Offset for data I/O */
411#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
412/* Offset for normal register accesses */
413#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
414/* Offset for alternate registers */
415#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
416/* Interval between registers */
417#define CONFIG_SYS_ATA_STRIDE 4
418#define CONFIG_ATAPI 1
419
420/* we enable IDE and FAT support, so we also need partition support */
421#define CONFIG_DOS_PARTITION 1
422
423/*
424 * Open Firmware flat tree
425 */
426#define CONFIG_OF_LIBFDT 1
427#define CONFIG_OF_BOARD_SETUP 1
428
429#define OF_CPU "PowerPC,5200@0"
430#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
431#define OF_SOC "soc5200@f0000000"
432#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
433
434#endif /* __CONFIG_H */