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Kevin Scholz3bb3f262019-10-07 19:26:36 +05301/* SPDX-License-Identifier: BSD-3-Clause */
Dave Gerlacha8c13c72021-05-11 10:22:11 -05002/*
3 * Cadence DDR Driver
4 *
5 * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
6 * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
Kevin Scholz3bb3f262019-10-07 19:26:36 +05307 */
Dave Gerlacha8c13c72021-05-11 10:22:11 -05008
9#ifndef lpddr4_obj_if_h
10#define lpddr4_obj_if_h
Kevin Scholz3bb3f262019-10-07 19:26:36 +053011
12#include "lpddr4_if.h"
13
Dave Gerlacha8c13c72021-05-11 10:22:11 -050014typedef struct lpddr4_obj_s {
15 u32 (*probe)(const lpddr4_config *config, u16 *configsize);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053016
Dave Gerlacha8c13c72021-05-11 10:22:11 -050017 u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053018
Dave Gerlacha8c13c72021-05-11 10:22:11 -050019 u32 (*start)(const lpddr4_privatedata *pd);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053020
Dave Gerlacha8c13c72021-05-11 10:22:11 -050021 u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053022
Dave Gerlacha8c13c72021-05-11 10:22:11 -050023 u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053024
Dave Gerlacha8c13c72021-05-11 10:22:11 -050025 u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053026
Dave Gerlacha8c13c72021-05-11 10:22:11 -050027 u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053028
Dave Gerlacha8c13c72021-05-11 10:22:11 -050029 u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053030
Dave Gerlacha8c13c72021-05-11 10:22:11 -050031 u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053032
Dave Gerlacha8c13c72021-05-11 10:22:11 -050033 u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053034
Dave Gerlacha8c13c72021-05-11 10:22:11 -050035 u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053036
Dave Gerlacha8c13c72021-05-11 10:22:11 -050037 u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053038
Dave Gerlacha8c13c72021-05-11 10:22:11 -050039 u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053040
Dave Gerlacha8c13c72021-05-11 10:22:11 -050041 u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053042
Dave Gerlacha8c13c72021-05-11 10:22:11 -050043 u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053044
Dave Gerlacha8c13c72021-05-11 10:22:11 -050045 u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053046
Dave Gerlacha8c13c72021-05-11 10:22:11 -050047 u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053048
Dave Gerlacha8c13c72021-05-11 10:22:11 -050049 u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053050
Dave Gerlacha8c13c72021-05-11 10:22:11 -050051 u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053052
Dave Gerlacha8c13c72021-05-11 10:22:11 -050053 u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053054
Dave Gerlacha8c13c72021-05-11 10:22:11 -050055 u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053056
Dave Gerlacha8c13c72021-05-11 10:22:11 -050057 u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053058
Dave Gerlacha8c13c72021-05-11 10:22:11 -050059 u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053060
Dave Gerlacha8c13c72021-05-11 10:22:11 -050061 u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053062
Dave Gerlacha8c13c72021-05-11 10:22:11 -050063 u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053064
Dave Gerlacha8c13c72021-05-11 10:22:11 -050065 u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053066
Dave Gerlacha8c13c72021-05-11 10:22:11 -050067 u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053068
Dave Gerlacha8c13c72021-05-11 10:22:11 -050069 u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053070
Dave Gerlacha8c13c72021-05-11 10:22:11 -050071 u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053072
Dave Gerlacha8c13c72021-05-11 10:22:11 -050073 u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053074
Dave Gerlacha8c13c72021-05-11 10:22:11 -050075 u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053076
Dave Gerlacha8c13c72021-05-11 10:22:11 -050077 u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053078
Dave Gerlacha8c13c72021-05-11 10:22:11 -050079 u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053080
Dave Gerlacha8c13c72021-05-11 10:22:11 -050081 u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
82} lpddr4_obj;
Kevin Scholz3bb3f262019-10-07 19:26:36 +053083
Dave Gerlacha8c13c72021-05-11 10:22:11 -050084extern lpddr4_obj *lpddr4_getinstance(void);
Kevin Scholz3bb3f262019-10-07 19:26:36 +053085
Dave Gerlacha8c13c72021-05-11 10:22:11 -050086#endif /* lpddr4_obj_if_h */