blob: 9d255cf95ff647e4c9faecc0d3fc84fb376da7f3 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002/*
3 * Copyright (c) 2016, NVIDIA CORPORATION.
4 *
Stephen Warrenba4dfef2016-10-21 14:46:47 -06005 * Portions based on U-Boot's rtl8169.c.
6 */
7
8/*
9 * This driver supports the Synopsys Designware Ethernet QOS (Quality Of
10 * Service) IP block. The IP supports multiple options for bus type, clocking/
11 * reset structure, and feature list.
12 *
13 * The driver is written such that generic core logic is kept separate from
14 * configuration-specific logic. Code that interacts with configuration-
15 * specific resources is split out into separate functions to avoid polluting
16 * common code. If/when this driver is enhanced to support multiple
17 * configurations, the core code should be adapted to call all configuration-
18 * specific functions through function pointers, with the definition of those
19 * function pointers being supplied by struct udevice_id eqos_ids[]'s .data
20 * field.
21 *
22 * The following configurations are currently supported:
23 * tegra186:
24 * NVIDIA's Tegra186 chip. This configuration uses an AXI master/DMA bus, an
25 * AHB slave/register bus, contains the DMA, MTL, and MAC sub-blocks, and
26 * supports a single RGMII PHY. This configuration also has SW control over
27 * all clock and reset signals to the HW block.
28 */
Patrick Delaunaycafaa302020-09-09 18:30:06 +020029
Patrick Delaunayb547f4b2021-07-20 20:15:29 +020030#define LOG_CATEGORY UCLASS_ETH
31
Stephen Warrenba4dfef2016-10-21 14:46:47 -060032#include <common.h>
33#include <clk.h>
Simon Glass1eb69ae2019-11-14 12:57:39 -070034#include <cpu_func.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060035#include <dm.h>
36#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060037#include <log.h>
Simon Glass336d4612020-02-03 07:36:16 -070038#include <malloc.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060039#include <memalign.h>
40#include <miiphy.h>
41#include <net.h>
42#include <netdev.h>
43#include <phy.h>
44#include <reset.h>
45#include <wait_bit.h>
Simon Glass90526e92020-05-10 11:39:56 -060046#include <asm/cache.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060047#include <asm/gpio.h>
48#include <asm/io.h>
Ye Li6a895d02020-05-03 22:41:15 +080049#include <eth_phy.h>
Fugang Duan0e9d2392020-05-03 22:41:18 +080050#ifdef CONFIG_ARCH_IMX8M
51#include <asm/arch/clock.h>
52#include <asm/mach-imx/sys_proto.h>
53#endif
Simon Glasscd93d622020-05-10 11:40:13 -060054#include <linux/bitops.h>
Simon Glassc05ed002020-05-10 11:40:11 -060055#include <linux/delay.h>
Stephen Warrenba4dfef2016-10-21 14:46:47 -060056
57/* Core registers */
58
59#define EQOS_MAC_REGS_BASE 0x000
60struct eqos_mac_regs {
61 uint32_t configuration; /* 0x000 */
62 uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
63 uint32_t q0_tx_flow_ctrl; /* 0x070 */
64 uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
65 uint32_t rx_flow_ctrl; /* 0x090 */
66 uint32_t unused_094; /* 0x094 */
67 uint32_t txq_prty_map0; /* 0x098 */
68 uint32_t unused_09c; /* 0x09c */
69 uint32_t rxq_ctrl0; /* 0x0a0 */
70 uint32_t unused_0a4; /* 0x0a4 */
71 uint32_t rxq_ctrl2; /* 0x0a8 */
72 uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
73 uint32_t us_tic_counter; /* 0x0dc */
74 uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
75 uint32_t hw_feature0; /* 0x11c */
76 uint32_t hw_feature1; /* 0x120 */
77 uint32_t hw_feature2; /* 0x124 */
78 uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
79 uint32_t mdio_address; /* 0x200 */
80 uint32_t mdio_data; /* 0x204 */
81 uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
82 uint32_t address0_high; /* 0x300 */
83 uint32_t address0_low; /* 0x304 */
84};
85
86#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
87#define EQOS_MAC_CONFIGURATION_CST BIT(21)
88#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
89#define EQOS_MAC_CONFIGURATION_WD BIT(19)
90#define EQOS_MAC_CONFIGURATION_JD BIT(17)
91#define EQOS_MAC_CONFIGURATION_JE BIT(16)
92#define EQOS_MAC_CONFIGURATION_PS BIT(15)
93#define EQOS_MAC_CONFIGURATION_FES BIT(14)
94#define EQOS_MAC_CONFIGURATION_DM BIT(13)
Fugang Duan3a97da12020-05-03 22:41:17 +080095#define EQOS_MAC_CONFIGURATION_LM BIT(12)
Stephen Warrenba4dfef2016-10-21 14:46:47 -060096#define EQOS_MAC_CONFIGURATION_TE BIT(1)
97#define EQOS_MAC_CONFIGURATION_RE BIT(0)
98
99#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
100#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
101#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
102
103#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
104
105#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
106#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
107
108#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
109#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
110#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
111#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200112#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV 1
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600113
114#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
115#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
116
Fugang Duan3a97da12020-05-03 22:41:17 +0800117#define EQOS_MAC_HW_FEATURE0_MMCSEL_SHIFT 8
118#define EQOS_MAC_HW_FEATURE0_HDSEL_SHIFT 2
119#define EQOS_MAC_HW_FEATURE0_GMIISEL_SHIFT 1
120#define EQOS_MAC_HW_FEATURE0_MIISEL_SHIFT 0
121
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600122#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
123#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
124#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
125#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
126
Fugang Duan3a97da12020-05-03 22:41:17 +0800127#define EQOS_MAC_HW_FEATURE3_ASP_SHIFT 28
128#define EQOS_MAC_HW_FEATURE3_ASP_MASK 0x3
129
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600130#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
131#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
132#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
133#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200134#define EQOS_MAC_MDIO_ADDRESS_CR_250_300 5
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600135#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
136#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
137#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
138#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
139#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
140#define EQOS_MAC_MDIO_ADDRESS_GB BIT(0)
141
142#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
143
144#define EQOS_MTL_REGS_BASE 0xd00
145struct eqos_mtl_regs {
146 uint32_t txq0_operation_mode; /* 0xd00 */
147 uint32_t unused_d04; /* 0xd04 */
148 uint32_t txq0_debug; /* 0xd08 */
149 uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
150 uint32_t txq0_quantum_weight; /* 0xd18 */
151 uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
152 uint32_t rxq0_operation_mode; /* 0xd30 */
153 uint32_t unused_d34; /* 0xd34 */
154 uint32_t rxq0_debug; /* 0xd38 */
155};
156
157#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
158#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
159#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
160#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
161#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
162#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
163#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
164
165#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
166#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
167#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
168
169#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
170#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
171#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
172#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
173#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
174#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
175#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
176#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
177
178#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
179#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
180#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
181#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
182
183#define EQOS_DMA_REGS_BASE 0x1000
184struct eqos_dma_regs {
185 uint32_t mode; /* 0x1000 */
186 uint32_t sysbus_mode; /* 0x1004 */
187 uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
188 uint32_t ch0_control; /* 0x1100 */
189 uint32_t ch0_tx_control; /* 0x1104 */
190 uint32_t ch0_rx_control; /* 0x1108 */
191 uint32_t unused_110c; /* 0x110c */
192 uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
193 uint32_t ch0_txdesc_list_address; /* 0x1114 */
194 uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
195 uint32_t ch0_rxdesc_list_address; /* 0x111c */
196 uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
197 uint32_t unused_1124; /* 0x1124 */
198 uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
199 uint32_t ch0_txdesc_ring_length; /* 0x112c */
200 uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
201};
202
203#define EQOS_DMA_MODE_SWR BIT(0)
204
205#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
206#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
207#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
208#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
209#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
210#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
211
Marek Vasut6f1e6682021-01-07 11:12:16 +0100212#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT 18
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600213#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
214
215#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
216#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
217#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
218#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
219
220#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
221#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
222#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
223#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
224#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
225
226/* These registers are Tegra186-specific */
227#define EQOS_TEGRA186_REGS_BASE 0x8800
228struct eqos_tegra186_regs {
229 uint32_t sdmemcomppadctrl; /* 0x8800 */
230 uint32_t auto_cal_config; /* 0x8804 */
231 uint32_t unused_8808; /* 0x8808 */
232 uint32_t auto_cal_status; /* 0x880c */
233};
234
235#define EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD BIT(31)
236
237#define EQOS_AUTO_CAL_CONFIG_START BIT(31)
238#define EQOS_AUTO_CAL_CONFIG_ENABLE BIT(29)
239
240#define EQOS_AUTO_CAL_STATUS_ACTIVE BIT(31)
241
242/* Descriptors */
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600243#define EQOS_DESCRIPTORS_TX 4
244#define EQOS_DESCRIPTORS_RX 4
245#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600246#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
247#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
248#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
249
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600250struct eqos_desc {
251 u32 des0;
252 u32 des1;
253 u32 des2;
254 u32 des3;
255};
256
257#define EQOS_DESC3_OWN BIT(31)
258#define EQOS_DESC3_FD BIT(29)
259#define EQOS_DESC3_LD BIT(28)
260#define EQOS_DESC3_BUF1V BIT(24)
261
Marek Vasut6f1e6682021-01-07 11:12:16 +0100262#define EQOS_AXI_WIDTH_32 4
263#define EQOS_AXI_WIDTH_64 8
264#define EQOS_AXI_WIDTH_128 16
265
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600266struct eqos_config {
267 bool reg_access_always_ok;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200268 int mdio_wait;
269 int swr_wait;
270 int config_mac;
271 int config_mac_mdio;
Marek Vasut6f1e6682021-01-07 11:12:16 +0100272 unsigned int axi_bus_width;
Marek BehĂșn123ca112022-04-07 00:33:01 +0200273 phy_interface_t (*interface)(const struct udevice *dev);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200274 struct eqos_ops *ops;
275};
276
277struct eqos_ops {
278 void (*eqos_inval_desc)(void *desc);
279 void (*eqos_flush_desc)(void *desc);
280 void (*eqos_inval_buffer)(void *buf, size_t size);
281 void (*eqos_flush_buffer)(void *buf, size_t size);
282 int (*eqos_probe_resources)(struct udevice *dev);
283 int (*eqos_remove_resources)(struct udevice *dev);
284 int (*eqos_stop_resets)(struct udevice *dev);
285 int (*eqos_start_resets)(struct udevice *dev);
Patrick Delaunayc6a0df22021-07-20 20:09:56 +0200286 int (*eqos_stop_clks)(struct udevice *dev);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200287 int (*eqos_start_clks)(struct udevice *dev);
288 int (*eqos_calibrate_pads)(struct udevice *dev);
289 int (*eqos_disable_calibration)(struct udevice *dev);
290 int (*eqos_set_tx_clk_speed)(struct udevice *dev);
291 ulong (*eqos_get_tick_clk_rate)(struct udevice *dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600292};
293
294struct eqos_priv {
295 struct udevice *dev;
296 const struct eqos_config *config;
297 fdt_addr_t regs;
298 struct eqos_mac_regs *mac_regs;
299 struct eqos_mtl_regs *mtl_regs;
300 struct eqos_dma_regs *dma_regs;
301 struct eqos_tegra186_regs *tegra186_regs;
302 struct reset_ctl reset_ctl;
303 struct gpio_desc phy_reset_gpio;
304 struct clk clk_master_bus;
305 struct clk clk_rx;
306 struct clk clk_ptp_ref;
307 struct clk clk_tx;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200308 struct clk clk_ck;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600309 struct clk clk_slave_bus;
310 struct mii_dev *mii;
311 struct phy_device *phy;
Patrick Delaunay4f60a512020-03-18 10:50:16 +0100312 u32 max_speed;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600313 void *descs;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600314 int tx_desc_idx, rx_desc_idx;
Marek Vasut6f1e6682021-01-07 11:12:16 +0100315 unsigned int desc_size;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600316 void *tx_dma_buf;
317 void *rx_dma_buf;
318 void *rx_pkt;
319 bool started;
320 bool reg_access_ok;
Daniil Stas07292f82021-05-23 22:24:48 +0000321 bool clk_ck_enabled;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600322};
323
324/*
325 * TX and RX descriptors are 16 bytes. This causes problems with the cache
326 * maintenance on CPUs where the cache-line size exceeds the size of these
327 * descriptors. What will happen is that when the driver receives a packet
328 * it will be immediately requeued for the hardware to reuse. The CPU will
329 * therefore need to flush the cache-line containing the descriptor, which
330 * will cause all other descriptors in the same cache-line to be flushed
331 * along with it. If one of those descriptors had been written to by the
332 * device those changes (and the associated packet) will be lost.
333 *
334 * To work around this, we make use of non-cached memory if available. If
335 * descriptors are mapped uncached there's no need to manually flush them
336 * or invalidate them.
337 *
338 * Note that this only applies to descriptors. The packet data buffers do
339 * not have the same constraints since they are 1536 bytes large, so they
340 * are unlikely to share cache-lines.
341 */
Marek Vasut6f1e6682021-01-07 11:12:16 +0100342static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600343{
Marek Vasut6f1e6682021-01-07 11:12:16 +0100344 eqos->desc_size = ALIGN(sizeof(struct eqos_desc),
345 (unsigned int)ARCH_DMA_MINALIGN);
346
347 return memalign(eqos->desc_size, num * eqos->desc_size);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600348}
349
350static void eqos_free_descs(void *descs)
351{
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600352 free(descs);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600353}
354
Marek Vasut6f1e6682021-01-07 11:12:16 +0100355static struct eqos_desc *eqos_get_desc(struct eqos_priv *eqos,
356 unsigned int num, bool rx)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600357{
Marek Vasut6f1e6682021-01-07 11:12:16 +0100358 return eqos->descs +
359 ((rx ? EQOS_DESCRIPTORS_TX : 0) + num) * eqos->desc_size;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600360}
361
Fugang Duan3a97da12020-05-03 22:41:17 +0800362static void eqos_inval_desc_generic(void *desc)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200363{
Marek Vasut6f1e6682021-01-07 11:12:16 +0100364 unsigned long start = (unsigned long)desc;
365 unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
366 ARCH_DMA_MINALIGN);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200367
368 invalidate_dcache_range(start, end);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600369}
370
Fugang Duan3a97da12020-05-03 22:41:17 +0800371static void eqos_flush_desc_generic(void *desc)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200372{
Marek Vasut6f1e6682021-01-07 11:12:16 +0100373 unsigned long start = (unsigned long)desc;
374 unsigned long end = ALIGN(start + sizeof(struct eqos_desc),
375 ARCH_DMA_MINALIGN);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200376
377 flush_dcache_range(start, end);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200378}
379
380static void eqos_inval_buffer_tegra186(void *buf, size_t size)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600381{
382 unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
383 unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
384
385 invalidate_dcache_range(start, end);
386}
387
Fugang Duan3a97da12020-05-03 22:41:17 +0800388static void eqos_inval_buffer_generic(void *buf, size_t size)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200389{
390 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
391 unsigned long end = roundup((unsigned long)buf + size,
392 ARCH_DMA_MINALIGN);
393
394 invalidate_dcache_range(start, end);
395}
396
397static void eqos_flush_buffer_tegra186(void *buf, size_t size)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600398{
399 flush_cache((unsigned long)buf, size);
400}
401
Fugang Duan3a97da12020-05-03 22:41:17 +0800402static void eqos_flush_buffer_generic(void *buf, size_t size)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200403{
404 unsigned long start = rounddown((unsigned long)buf, ARCH_DMA_MINALIGN);
405 unsigned long end = roundup((unsigned long)buf + size,
406 ARCH_DMA_MINALIGN);
407
408 flush_dcache_range(start, end);
409}
410
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600411static int eqos_mdio_wait_idle(struct eqos_priv *eqos)
412{
Álvaro Fernåndez Rojas48263502018-01-23 17:14:55 +0100413 return wait_for_bit_le32(&eqos->mac_regs->mdio_address,
414 EQOS_MAC_MDIO_ADDRESS_GB, false,
415 1000000, true);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600416}
417
418static int eqos_mdio_read(struct mii_dev *bus, int mdio_addr, int mdio_devad,
419 int mdio_reg)
420{
421 struct eqos_priv *eqos = bus->priv;
422 u32 val;
423 int ret;
424
425 debug("%s(dev=%p, addr=%x, reg=%d):\n", __func__, eqos->dev, mdio_addr,
426 mdio_reg);
427
428 ret = eqos_mdio_wait_idle(eqos);
429 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900430 pr_err("MDIO not idle at entry");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600431 return ret;
432 }
433
434 val = readl(&eqos->mac_regs->mdio_address);
435 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
436 EQOS_MAC_MDIO_ADDRESS_C45E;
437 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
438 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200439 (eqos->config->config_mac_mdio <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600440 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
441 (EQOS_MAC_MDIO_ADDRESS_GOC_READ <<
442 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
443 EQOS_MAC_MDIO_ADDRESS_GB;
444 writel(val, &eqos->mac_regs->mdio_address);
445
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200446 udelay(eqos->config->mdio_wait);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600447
448 ret = eqos_mdio_wait_idle(eqos);
449 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900450 pr_err("MDIO read didn't complete");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600451 return ret;
452 }
453
454 val = readl(&eqos->mac_regs->mdio_data);
455 val &= EQOS_MAC_MDIO_DATA_GD_MASK;
456
457 debug("%s: val=%x\n", __func__, val);
458
459 return val;
460}
461
462static int eqos_mdio_write(struct mii_dev *bus, int mdio_addr, int mdio_devad,
463 int mdio_reg, u16 mdio_val)
464{
465 struct eqos_priv *eqos = bus->priv;
466 u32 val;
467 int ret;
468
469 debug("%s(dev=%p, addr=%x, reg=%d, val=%x):\n", __func__, eqos->dev,
470 mdio_addr, mdio_reg, mdio_val);
471
472 ret = eqos_mdio_wait_idle(eqos);
473 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900474 pr_err("MDIO not idle at entry");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600475 return ret;
476 }
477
478 writel(mdio_val, &eqos->mac_regs->mdio_data);
479
480 val = readl(&eqos->mac_regs->mdio_address);
481 val &= EQOS_MAC_MDIO_ADDRESS_SKAP |
482 EQOS_MAC_MDIO_ADDRESS_C45E;
483 val |= (mdio_addr << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
484 (mdio_reg << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200485 (eqos->config->config_mac_mdio <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600486 EQOS_MAC_MDIO_ADDRESS_CR_SHIFT) |
487 (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE <<
488 EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT) |
489 EQOS_MAC_MDIO_ADDRESS_GB;
490 writel(val, &eqos->mac_regs->mdio_address);
491
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200492 udelay(eqos->config->mdio_wait);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600493
494 ret = eqos_mdio_wait_idle(eqos);
495 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900496 pr_err("MDIO read didn't complete");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600497 return ret;
498 }
499
500 return 0;
501}
502
503static int eqos_start_clks_tegra186(struct udevice *dev)
504{
Fugang Duan3a97da12020-05-03 22:41:17 +0800505#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600506 struct eqos_priv *eqos = dev_get_priv(dev);
507 int ret;
508
509 debug("%s(dev=%p):\n", __func__, dev);
510
511 ret = clk_enable(&eqos->clk_slave_bus);
512 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900513 pr_err("clk_enable(clk_slave_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600514 goto err;
515 }
516
517 ret = clk_enable(&eqos->clk_master_bus);
518 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900519 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600520 goto err_disable_clk_slave_bus;
521 }
522
523 ret = clk_enable(&eqos->clk_rx);
524 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900525 pr_err("clk_enable(clk_rx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600526 goto err_disable_clk_master_bus;
527 }
528
529 ret = clk_enable(&eqos->clk_ptp_ref);
530 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900531 pr_err("clk_enable(clk_ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600532 goto err_disable_clk_rx;
533 }
534
535 ret = clk_set_rate(&eqos->clk_ptp_ref, 125 * 1000 * 1000);
536 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900537 pr_err("clk_set_rate(clk_ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600538 goto err_disable_clk_ptp_ref;
539 }
540
541 ret = clk_enable(&eqos->clk_tx);
542 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900543 pr_err("clk_enable(clk_tx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600544 goto err_disable_clk_ptp_ref;
545 }
Fugang Duan3a97da12020-05-03 22:41:17 +0800546#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600547
548 debug("%s: OK\n", __func__);
549 return 0;
550
Fugang Duan3a97da12020-05-03 22:41:17 +0800551#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600552err_disable_clk_ptp_ref:
553 clk_disable(&eqos->clk_ptp_ref);
554err_disable_clk_rx:
555 clk_disable(&eqos->clk_rx);
556err_disable_clk_master_bus:
557 clk_disable(&eqos->clk_master_bus);
558err_disable_clk_slave_bus:
559 clk_disable(&eqos->clk_slave_bus);
560err:
561 debug("%s: FAILED: %d\n", __func__, ret);
562 return ret;
Fugang Duan3a97da12020-05-03 22:41:17 +0800563#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600564}
565
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200566static int eqos_start_clks_stm32(struct udevice *dev)
567{
Fugang Duan3a97da12020-05-03 22:41:17 +0800568#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200569 struct eqos_priv *eqos = dev_get_priv(dev);
570 int ret;
571
572 debug("%s(dev=%p):\n", __func__, dev);
573
574 ret = clk_enable(&eqos->clk_master_bus);
575 if (ret < 0) {
576 pr_err("clk_enable(clk_master_bus) failed: %d", ret);
577 goto err;
578 }
579
580 ret = clk_enable(&eqos->clk_rx);
581 if (ret < 0) {
582 pr_err("clk_enable(clk_rx) failed: %d", ret);
583 goto err_disable_clk_master_bus;
584 }
585
586 ret = clk_enable(&eqos->clk_tx);
587 if (ret < 0) {
588 pr_err("clk_enable(clk_tx) failed: %d", ret);
589 goto err_disable_clk_rx;
590 }
591
Daniil Stas07292f82021-05-23 22:24:48 +0000592 if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200593 ret = clk_enable(&eqos->clk_ck);
594 if (ret < 0) {
595 pr_err("clk_enable(clk_ck) failed: %d", ret);
596 goto err_disable_clk_tx;
597 }
Daniil Stas07292f82021-05-23 22:24:48 +0000598 eqos->clk_ck_enabled = true;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200599 }
Fugang Duan3a97da12020-05-03 22:41:17 +0800600#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200601
602 debug("%s: OK\n", __func__);
603 return 0;
604
Fugang Duan3a97da12020-05-03 22:41:17 +0800605#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200606err_disable_clk_tx:
607 clk_disable(&eqos->clk_tx);
608err_disable_clk_rx:
609 clk_disable(&eqos->clk_rx);
610err_disable_clk_master_bus:
611 clk_disable(&eqos->clk_master_bus);
612err:
613 debug("%s: FAILED: %d\n", __func__, ret);
614 return ret;
Fugang Duan3a97da12020-05-03 22:41:17 +0800615#endif
616}
617
Patrick Delaunayc6a0df22021-07-20 20:09:56 +0200618static int eqos_stop_clks_tegra186(struct udevice *dev)
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600619{
Fugang Duan3a97da12020-05-03 22:41:17 +0800620#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600621 struct eqos_priv *eqos = dev_get_priv(dev);
622
623 debug("%s(dev=%p):\n", __func__, dev);
624
625 clk_disable(&eqos->clk_tx);
626 clk_disable(&eqos->clk_ptp_ref);
627 clk_disable(&eqos->clk_rx);
628 clk_disable(&eqos->clk_master_bus);
629 clk_disable(&eqos->clk_slave_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800630#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600631
632 debug("%s: OK\n", __func__);
Patrick Delaunayc6a0df22021-07-20 20:09:56 +0200633 return 0;
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600634}
635
Patrick Delaunayc6a0df22021-07-20 20:09:56 +0200636static int eqos_stop_clks_stm32(struct udevice *dev)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200637{
Fugang Duan3a97da12020-05-03 22:41:17 +0800638#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200639 struct eqos_priv *eqos = dev_get_priv(dev);
640
641 debug("%s(dev=%p):\n", __func__, dev);
642
643 clk_disable(&eqos->clk_tx);
644 clk_disable(&eqos->clk_rx);
645 clk_disable(&eqos->clk_master_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800646#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200647
648 debug("%s: OK\n", __func__);
Patrick Delaunayc6a0df22021-07-20 20:09:56 +0200649 return 0;
Fugang Duan3a97da12020-05-03 22:41:17 +0800650}
651
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600652static int eqos_start_resets_tegra186(struct udevice *dev)
653{
654 struct eqos_priv *eqos = dev_get_priv(dev);
655 int ret;
656
657 debug("%s(dev=%p):\n", __func__, dev);
658
659 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
660 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900661 pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600662 return ret;
663 }
664
665 udelay(2);
666
667 ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
668 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900669 pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600670 return ret;
671 }
672
673 ret = reset_assert(&eqos->reset_ctl);
674 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900675 pr_err("reset_assert() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600676 return ret;
677 }
678
679 udelay(2);
680
681 ret = reset_deassert(&eqos->reset_ctl);
682 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900683 pr_err("reset_deassert() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600684 return ret;
685 }
686
687 debug("%s: OK\n", __func__);
688 return 0;
689}
690
691static int eqos_stop_resets_tegra186(struct udevice *dev)
692{
693 struct eqos_priv *eqos = dev_get_priv(dev);
694
695 reset_assert(&eqos->reset_ctl);
696 dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
697
698 return 0;
699}
700
701static int eqos_calibrate_pads_tegra186(struct udevice *dev)
702{
703 struct eqos_priv *eqos = dev_get_priv(dev);
704 int ret;
705
706 debug("%s(dev=%p):\n", __func__, dev);
707
708 setbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
709 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
710
711 udelay(1);
712
713 setbits_le32(&eqos->tegra186_regs->auto_cal_config,
714 EQOS_AUTO_CAL_CONFIG_START | EQOS_AUTO_CAL_CONFIG_ENABLE);
715
Álvaro Fernåndez Rojas48263502018-01-23 17:14:55 +0100716 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
717 EQOS_AUTO_CAL_STATUS_ACTIVE, true, 10, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600718 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900719 pr_err("calibrate didn't start");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600720 goto failed;
721 }
722
Álvaro Fernåndez Rojas48263502018-01-23 17:14:55 +0100723 ret = wait_for_bit_le32(&eqos->tegra186_regs->auto_cal_status,
724 EQOS_AUTO_CAL_STATUS_ACTIVE, false, 10, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600725 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900726 pr_err("calibrate didn't finish");
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600727 goto failed;
728 }
729
730 ret = 0;
731
732failed:
733 clrbits_le32(&eqos->tegra186_regs->sdmemcomppadctrl,
734 EQOS_SDMEMCOMPPADCTRL_PAD_E_INPUT_OR_E_PWRD);
735
736 debug("%s: returns %d\n", __func__, ret);
737
738 return ret;
739}
740
741static int eqos_disable_calibration_tegra186(struct udevice *dev)
742{
743 struct eqos_priv *eqos = dev_get_priv(dev);
744
745 debug("%s(dev=%p):\n", __func__, dev);
746
747 clrbits_le32(&eqos->tegra186_regs->auto_cal_config,
748 EQOS_AUTO_CAL_CONFIG_ENABLE);
749
750 return 0;
751}
752
753static ulong eqos_get_tick_clk_rate_tegra186(struct udevice *dev)
754{
Fugang Duan3a97da12020-05-03 22:41:17 +0800755#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600756 struct eqos_priv *eqos = dev_get_priv(dev);
757
758 return clk_get_rate(&eqos->clk_slave_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800759#else
760 return 0;
761#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600762}
763
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200764static ulong eqos_get_tick_clk_rate_stm32(struct udevice *dev)
765{
Fugang Duan3a97da12020-05-03 22:41:17 +0800766#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200767 struct eqos_priv *eqos = dev_get_priv(dev);
768
769 return clk_get_rate(&eqos->clk_master_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +0800770#else
771 return 0;
772#endif
773}
774
Fugang Duan0e9d2392020-05-03 22:41:18 +0800775__weak u32 imx_get_eqos_csr_clk(void)
776{
777 return 100 * 1000000;
778}
779__weak int imx_eqos_txclk_set_rate(unsigned long rate)
780{
781 return 0;
782}
783
Fugang Duan3a97da12020-05-03 22:41:17 +0800784static ulong eqos_get_tick_clk_rate_imx(struct udevice *dev)
785{
Fugang Duan0e9d2392020-05-03 22:41:18 +0800786 return imx_get_eqos_csr_clk();
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200787}
788
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600789static int eqos_set_full_duplex(struct udevice *dev)
790{
791 struct eqos_priv *eqos = dev_get_priv(dev);
792
793 debug("%s(dev=%p):\n", __func__, dev);
794
795 setbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
796
797 return 0;
798}
799
800static int eqos_set_half_duplex(struct udevice *dev)
801{
802 struct eqos_priv *eqos = dev_get_priv(dev);
803
804 debug("%s(dev=%p):\n", __func__, dev);
805
806 clrbits_le32(&eqos->mac_regs->configuration, EQOS_MAC_CONFIGURATION_DM);
807
808 /* WAR: Flush TX queue when switching to half-duplex */
809 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
810 EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
811
812 return 0;
813}
814
815static int eqos_set_gmii_speed(struct udevice *dev)
816{
817 struct eqos_priv *eqos = dev_get_priv(dev);
818
819 debug("%s(dev=%p):\n", __func__, dev);
820
821 clrbits_le32(&eqos->mac_regs->configuration,
822 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
823
824 return 0;
825}
826
827static int eqos_set_mii_speed_100(struct udevice *dev)
828{
829 struct eqos_priv *eqos = dev_get_priv(dev);
830
831 debug("%s(dev=%p):\n", __func__, dev);
832
833 setbits_le32(&eqos->mac_regs->configuration,
834 EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
835
836 return 0;
837}
838
839static int eqos_set_mii_speed_10(struct udevice *dev)
840{
841 struct eqos_priv *eqos = dev_get_priv(dev);
842
843 debug("%s(dev=%p):\n", __func__, dev);
844
845 clrsetbits_le32(&eqos->mac_regs->configuration,
846 EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
847
848 return 0;
849}
850
851static int eqos_set_tx_clk_speed_tegra186(struct udevice *dev)
852{
Fugang Duan3a97da12020-05-03 22:41:17 +0800853#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600854 struct eqos_priv *eqos = dev_get_priv(dev);
855 ulong rate;
856 int ret;
857
858 debug("%s(dev=%p):\n", __func__, dev);
859
860 switch (eqos->phy->speed) {
861 case SPEED_1000:
862 rate = 125 * 1000 * 1000;
863 break;
864 case SPEED_100:
865 rate = 25 * 1000 * 1000;
866 break;
867 case SPEED_10:
868 rate = 2.5 * 1000 * 1000;
869 break;
870 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900871 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600872 return -EINVAL;
873 }
874
875 ret = clk_set_rate(&eqos->clk_tx, rate);
876 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900877 pr_err("clk_set_rate(tx_clk, %lu) failed: %d", rate, ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600878 return ret;
879 }
Fugang Duan3a97da12020-05-03 22:41:17 +0800880#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600881
882 return 0;
883}
884
Fugang Duan3a97da12020-05-03 22:41:17 +0800885static int eqos_set_tx_clk_speed_imx(struct udevice *dev)
886{
Fugang Duan0e9d2392020-05-03 22:41:18 +0800887 struct eqos_priv *eqos = dev_get_priv(dev);
888 ulong rate;
889 int ret;
890
891 debug("%s(dev=%p):\n", __func__, dev);
892
893 switch (eqos->phy->speed) {
894 case SPEED_1000:
895 rate = 125 * 1000 * 1000;
896 break;
897 case SPEED_100:
898 rate = 25 * 1000 * 1000;
899 break;
900 case SPEED_10:
901 rate = 2.5 * 1000 * 1000;
902 break;
903 default:
904 pr_err("invalid speed %d", eqos->phy->speed);
905 return -EINVAL;
906 }
907
908 ret = imx_eqos_txclk_set_rate(rate);
909 if (ret < 0) {
910 pr_err("imx (tx_clk, %lu) failed: %d", rate, ret);
911 return ret;
912 }
913
Fugang Duan3a97da12020-05-03 22:41:17 +0800914 return 0;
915}
916
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600917static int eqos_adjust_link(struct udevice *dev)
918{
919 struct eqos_priv *eqos = dev_get_priv(dev);
920 int ret;
921 bool en_calibration;
922
923 debug("%s(dev=%p):\n", __func__, dev);
924
925 if (eqos->phy->duplex)
926 ret = eqos_set_full_duplex(dev);
927 else
928 ret = eqos_set_half_duplex(dev);
929 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900930 pr_err("eqos_set_*_duplex() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600931 return ret;
932 }
933
934 switch (eqos->phy->speed) {
935 case SPEED_1000:
936 en_calibration = true;
937 ret = eqos_set_gmii_speed(dev);
938 break;
939 case SPEED_100:
940 en_calibration = true;
941 ret = eqos_set_mii_speed_100(dev);
942 break;
943 case SPEED_10:
944 en_calibration = false;
945 ret = eqos_set_mii_speed_10(dev);
946 break;
947 default:
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900948 pr_err("invalid speed %d", eqos->phy->speed);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600949 return -EINVAL;
950 }
951 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900952 pr_err("eqos_set_*mii_speed*() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600953 return ret;
954 }
955
956 if (en_calibration) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200957 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600958 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200959 pr_err("eqos_calibrate_pads() failed: %d",
960 ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600961 return ret;
962 }
963 } else {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200964 ret = eqos->config->ops->eqos_disable_calibration(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600965 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200966 pr_err("eqos_disable_calibration() failed: %d",
967 ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600968 return ret;
969 }
970 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200971 ret = eqos->config->ops->eqos_set_tx_clk_speed(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600972 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +0200973 pr_err("eqos_set_tx_clk_speed() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600974 return ret;
975 }
976
977 return 0;
978}
979
980static int eqos_write_hwaddr(struct udevice *dev)
981{
Simon Glassc69cda22020-12-03 16:55:20 -0700982 struct eth_pdata *plat = dev_get_plat(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -0600983 struct eqos_priv *eqos = dev_get_priv(dev);
984 uint32_t val;
985
986 /*
987 * This function may be called before start() or after stop(). At that
988 * time, on at least some configurations of the EQoS HW, all clocks to
989 * the EQoS HW block will be stopped, and a reset signal applied. If
990 * any register access is attempted in this state, bus timeouts or CPU
991 * hangs may occur. This check prevents that.
992 *
993 * A simple solution to this problem would be to not implement
994 * write_hwaddr(), since start() always writes the MAC address into HW
995 * anyway. However, it is desirable to implement write_hwaddr() to
996 * support the case of SW that runs subsequent to U-Boot which expects
997 * the MAC address to already be programmed into the EQoS registers,
998 * which must happen irrespective of whether the U-Boot user (or
999 * scripts) actually made use of the EQoS device, and hence
1000 * irrespective of whether start() was ever called.
1001 *
1002 * Note that this requirement by subsequent SW is not valid for
1003 * Tegra186, and is likely not valid for any non-PCI instantiation of
1004 * the EQoS HW block. This function is implemented solely as
1005 * future-proofing with the expectation the driver will eventually be
1006 * ported to some system where the expectation above is true.
1007 */
1008 if (!eqos->config->reg_access_always_ok && !eqos->reg_access_ok)
1009 return 0;
1010
1011 /* Update the MAC address */
1012 val = (plat->enetaddr[5] << 8) |
1013 (plat->enetaddr[4]);
1014 writel(val, &eqos->mac_regs->address0_high);
1015 val = (plat->enetaddr[3] << 24) |
1016 (plat->enetaddr[2] << 16) |
1017 (plat->enetaddr[1] << 8) |
1018 (plat->enetaddr[0]);
1019 writel(val, &eqos->mac_regs->address0_low);
1020
1021 return 0;
1022}
1023
Ye Li580fab42020-05-03 22:41:20 +08001024static int eqos_read_rom_hwaddr(struct udevice *dev)
1025{
Simon Glassc69cda22020-12-03 16:55:20 -07001026 struct eth_pdata *pdata = dev_get_plat(dev);
Ye Li580fab42020-05-03 22:41:20 +08001027
1028#ifdef CONFIG_ARCH_IMX8M
Simon Glass552da332020-12-16 21:20:16 -07001029 imx_get_mac_from_fuse(dev_seq(dev), pdata->enetaddr);
Ye Li580fab42020-05-03 22:41:20 +08001030#endif
1031 return !is_valid_ethaddr(pdata->enetaddr);
1032}
1033
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001034static int eqos_start(struct udevice *dev)
1035{
1036 struct eqos_priv *eqos = dev_get_priv(dev);
1037 int ret, i;
1038 ulong rate;
1039 u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
1040 ulong last_rx_desc;
Marek Vasut6f1e6682021-01-07 11:12:16 +01001041 ulong desc_pad;
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001042
1043 debug("%s(dev=%p):\n", __func__, dev);
1044
1045 eqos->tx_desc_idx = 0;
1046 eqos->rx_desc_idx = 0;
1047
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001048 ret = eqos->config->ops->eqos_start_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001049 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001050 pr_err("eqos_start_resets() failed: %d", ret);
Marek Vasut3fbd17a2021-11-13 03:23:52 +01001051 goto err;
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001052 }
1053
1054 udelay(10);
1055
1056 eqos->reg_access_ok = true;
1057
Álvaro Fernåndez Rojas48263502018-01-23 17:14:55 +01001058 ret = wait_for_bit_le32(&eqos->dma_regs->mode,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001059 EQOS_DMA_MODE_SWR, false,
1060 eqos->config->swr_wait, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001061 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001062 pr_err("EQOS_DMA_MODE_SWR stuck");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001063 goto err_stop_resets;
1064 }
1065
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001066 ret = eqos->config->ops->eqos_calibrate_pads(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001067 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001068 pr_err("eqos_calibrate_pads() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001069 goto err_stop_resets;
1070 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001071 rate = eqos->config->ops->eqos_get_tick_clk_rate(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001072
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001073 val = (rate / 1000000) - 1;
1074 writel(val, &eqos->mac_regs->us_tic_counter);
1075
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001076 /*
1077 * if PHY was already connected and configured,
1078 * don't need to reconnect/reconfigure again
1079 */
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001080 if (!eqos->phy) {
Ye Li6a895d02020-05-03 22:41:15 +08001081 int addr = -1;
1082#ifdef CONFIG_DM_ETH_PHY
1083 addr = eth_phy_get_addr(dev);
1084#endif
1085#ifdef DWC_NET_PHYADDR
1086 addr = DWC_NET_PHYADDR;
1087#endif
1088 eqos->phy = phy_connect(eqos->mii, addr, dev,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001089 eqos->config->interface(dev));
1090 if (!eqos->phy) {
1091 pr_err("phy_connect() failed");
1092 goto err_stop_resets;
1093 }
Patrick Delaunay4f60a512020-03-18 10:50:16 +01001094
1095 if (eqos->max_speed) {
1096 ret = phy_set_supported(eqos->phy, eqos->max_speed);
1097 if (ret) {
1098 pr_err("phy_set_supported() failed: %d", ret);
1099 goto err_shutdown_phy;
1100 }
1101 }
1102
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001103 ret = phy_config(eqos->phy);
1104 if (ret < 0) {
1105 pr_err("phy_config() failed: %d", ret);
1106 goto err_shutdown_phy;
1107 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001108 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001109
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001110 ret = phy_startup(eqos->phy);
1111 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001112 pr_err("phy_startup() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001113 goto err_shutdown_phy;
1114 }
1115
1116 if (!eqos->phy->link) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001117 pr_err("No link");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001118 goto err_shutdown_phy;
1119 }
1120
1121 ret = eqos_adjust_link(dev);
1122 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001123 pr_err("eqos_adjust_link() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001124 goto err_shutdown_phy;
1125 }
1126
1127 /* Configure MTL */
1128
1129 /* Enable Store and Forward mode for TX */
1130 /* Program Tx operating mode */
1131 setbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1132 EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
1133 (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
1134 EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
1135
1136 /* Transmit Queue weight */
1137 writel(0x10, &eqos->mtl_regs->txq0_quantum_weight);
1138
1139 /* Enable Store and Forward mode for RX, since no jumbo frame */
1140 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
Daniil Stasf024e0b2021-05-30 13:34:09 +00001141 EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001142
1143 /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
1144 val = readl(&eqos->mac_regs->hw_feature1);
1145 tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
1146 EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
1147 rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
1148 EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
1149
1150 /*
1151 * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
1152 * r/tqs is encoded as (n / 256) - 1.
1153 */
1154 tqs = (128 << tx_fifo_sz) / 256 - 1;
1155 rqs = (128 << rx_fifo_sz) / 256 - 1;
1156
1157 clrsetbits_le32(&eqos->mtl_regs->txq0_operation_mode,
1158 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
1159 EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
1160 tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
1161 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1162 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
1163 EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
1164 rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
1165
1166 /* Flow control used only if each channel gets 4KB or more FIFO */
1167 if (rqs >= ((4096 / 256) - 1)) {
1168 u32 rfd, rfa;
1169
1170 setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1171 EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
1172
1173 /*
1174 * Set Threshold for Activating Flow Contol space for min 2
1175 * frames ie, (1500 * 1) = 1500 bytes.
1176 *
1177 * Set Threshold for Deactivating Flow Contol for space of
1178 * min 1 frame (frame size 1500bytes) in receive fifo
1179 */
1180 if (rqs == ((4096 / 256) - 1)) {
1181 /*
1182 * This violates the above formula because of FIFO size
1183 * limit therefore overflow may occur inspite of this.
1184 */
1185 rfd = 0x3; /* Full-3K */
1186 rfa = 0x1; /* Full-1.5K */
1187 } else if (rqs == ((8192 / 256) - 1)) {
1188 rfd = 0x6; /* Full-4K */
1189 rfa = 0xa; /* Full-6K */
1190 } else if (rqs == ((16384 / 256) - 1)) {
1191 rfd = 0x6; /* Full-4K */
1192 rfa = 0x12; /* Full-10K */
1193 } else {
1194 rfd = 0x6; /* Full-4K */
1195 rfa = 0x1E; /* Full-16K */
1196 }
1197
1198 clrsetbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
1199 (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
1200 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1201 (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
1202 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
1203 (rfd <<
1204 EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
1205 (rfa <<
1206 EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
1207 }
1208
1209 /* Configure MAC */
1210
1211 clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
1212 EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
1213 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001214 eqos->config->config_mac <<
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001215 EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
1216
Fugang Duan3a97da12020-05-03 22:41:17 +08001217 /* Multicast and Broadcast Queue Enable */
1218 setbits_le32(&eqos->mac_regs->unused_0a4,
1219 0x00100000);
1220 /* enable promise mode */
1221 setbits_le32(&eqos->mac_regs->unused_004[1],
1222 0x1);
1223
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001224 /* Set TX flow control parameters */
1225 /* Set Pause Time */
1226 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1227 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
1228 /* Assign priority for TX flow control */
1229 clrbits_le32(&eqos->mac_regs->txq_prty_map0,
1230 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
1231 EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
1232 /* Assign priority for RX flow control */
1233 clrbits_le32(&eqos->mac_regs->rxq_ctrl2,
1234 EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
1235 EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
1236 /* Enable flow control */
1237 setbits_le32(&eqos->mac_regs->q0_tx_flow_ctrl,
1238 EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
1239 setbits_le32(&eqos->mac_regs->rx_flow_ctrl,
1240 EQOS_MAC_RX_FLOW_CTRL_RFE);
1241
1242 clrsetbits_le32(&eqos->mac_regs->configuration,
1243 EQOS_MAC_CONFIGURATION_GPSLCE |
1244 EQOS_MAC_CONFIGURATION_WD |
1245 EQOS_MAC_CONFIGURATION_JD |
1246 EQOS_MAC_CONFIGURATION_JE,
1247 EQOS_MAC_CONFIGURATION_CST |
1248 EQOS_MAC_CONFIGURATION_ACS);
1249
1250 eqos_write_hwaddr(dev);
1251
1252 /* Configure DMA */
1253
1254 /* Enable OSP mode */
1255 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1256 EQOS_DMA_CH0_TX_CONTROL_OSP);
1257
1258 /* RX buffer size. Must be a multiple of bus width */
1259 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1260 EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
1261 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
1262 EQOS_MAX_PACKET_SIZE <<
1263 EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
1264
Marek Vasut6f1e6682021-01-07 11:12:16 +01001265 desc_pad = (eqos->desc_size - sizeof(struct eqos_desc)) /
1266 eqos->config->axi_bus_width;
1267
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001268 setbits_le32(&eqos->dma_regs->ch0_control,
Marek Vasut6f1e6682021-01-07 11:12:16 +01001269 EQOS_DMA_CH0_CONTROL_PBLX8 |
1270 (desc_pad << EQOS_DMA_CH0_CONTROL_DSL_SHIFT));
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001271
1272 /*
1273 * Burst length must be < 1/2 FIFO size.
1274 * FIFO size in tqs is encoded as (n / 256) - 1.
1275 * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
1276 * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
1277 */
1278 pbl = tqs + 1;
1279 if (pbl > 32)
1280 pbl = 32;
1281 clrsetbits_le32(&eqos->dma_regs->ch0_tx_control,
1282 EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
1283 EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
1284 pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
1285
1286 clrsetbits_le32(&eqos->dma_regs->ch0_rx_control,
1287 EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
1288 EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
1289 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
1290
1291 /* DMA performance configuration */
1292 val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
1293 EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
1294 EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
1295 writel(val, &eqos->dma_regs->sysbus_mode);
1296
1297 /* Set up descriptors */
1298
Marek Vasut6f1e6682021-01-07 11:12:16 +01001299 memset(eqos->descs, 0, eqos->desc_size * EQOS_DESCRIPTORS_NUM);
1300
1301 for (i = 0; i < EQOS_DESCRIPTORS_TX; i++) {
1302 struct eqos_desc *tx_desc = eqos_get_desc(eqos, i, false);
1303 eqos->config->ops->eqos_flush_desc(tx_desc);
1304 }
1305
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001306 for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
Marek Vasut6f1e6682021-01-07 11:12:16 +01001307 struct eqos_desc *rx_desc = eqos_get_desc(eqos, i, true);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001308 rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
1309 (i * EQOS_MAX_PACKET_SIZE));
Marek Vasut4332d802020-03-23 02:02:57 +01001310 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
Fugang Duan3a97da12020-05-03 22:41:17 +08001311 mb();
Marek Vasutdd90c2e2020-03-23 02:09:01 +01001312 eqos->config->ops->eqos_flush_desc(rx_desc);
Fugang Duan3a97da12020-05-03 22:41:17 +08001313 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf +
1314 (i * EQOS_MAX_PACKET_SIZE),
1315 EQOS_MAX_PACKET_SIZE);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001316 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001317
1318 writel(0, &eqos->dma_regs->ch0_txdesc_list_haddress);
Marek Vasut6f1e6682021-01-07 11:12:16 +01001319 writel((ulong)eqos_get_desc(eqos, 0, false),
1320 &eqos->dma_regs->ch0_txdesc_list_address);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001321 writel(EQOS_DESCRIPTORS_TX - 1,
1322 &eqos->dma_regs->ch0_txdesc_ring_length);
1323
1324 writel(0, &eqos->dma_regs->ch0_rxdesc_list_haddress);
Marek Vasut6f1e6682021-01-07 11:12:16 +01001325 writel((ulong)eqos_get_desc(eqos, 0, true),
1326 &eqos->dma_regs->ch0_rxdesc_list_address);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001327 writel(EQOS_DESCRIPTORS_RX - 1,
1328 &eqos->dma_regs->ch0_rxdesc_ring_length);
1329
1330 /* Enable everything */
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001331 setbits_le32(&eqos->dma_regs->ch0_tx_control,
1332 EQOS_DMA_CH0_TX_CONTROL_ST);
1333 setbits_le32(&eqos->dma_regs->ch0_rx_control,
1334 EQOS_DMA_CH0_RX_CONTROL_SR);
Fugang Duan3a97da12020-05-03 22:41:17 +08001335 setbits_le32(&eqos->mac_regs->configuration,
1336 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001337
1338 /* TX tail pointer not written until we need to TX a packet */
1339 /*
1340 * Point RX tail pointer at last descriptor. Ideally, we'd point at the
1341 * first descriptor, implying all descriptors were available. However,
1342 * that's not distinguishable from none of the descriptors being
1343 * available.
1344 */
Marek Vasut6f1e6682021-01-07 11:12:16 +01001345 last_rx_desc = (ulong)eqos_get_desc(eqos, EQOS_DESCRIPTORS_RX - 1, true);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001346 writel(last_rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1347
1348 eqos->started = true;
1349
1350 debug("%s: OK\n", __func__);
1351 return 0;
1352
1353err_shutdown_phy:
1354 phy_shutdown(eqos->phy);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001355err_stop_resets:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001356 eqos->config->ops->eqos_stop_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001357err:
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001358 pr_err("FAILED: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001359 return ret;
1360}
1361
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001362static void eqos_stop(struct udevice *dev)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001363{
1364 struct eqos_priv *eqos = dev_get_priv(dev);
1365 int i;
1366
1367 debug("%s(dev=%p):\n", __func__, dev);
1368
1369 if (!eqos->started)
1370 return;
1371 eqos->started = false;
1372 eqos->reg_access_ok = false;
1373
1374 /* Disable TX DMA */
1375 clrbits_le32(&eqos->dma_regs->ch0_tx_control,
1376 EQOS_DMA_CH0_TX_CONTROL_ST);
1377
1378 /* Wait for TX all packets to drain out of MTL */
1379 for (i = 0; i < 1000000; i++) {
1380 u32 val = readl(&eqos->mtl_regs->txq0_debug);
1381 u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
1382 EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
1383 u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
1384 if ((trcsts != 1) && (!txqsts))
1385 break;
1386 }
1387
1388 /* Turn off MAC TX and RX */
1389 clrbits_le32(&eqos->mac_regs->configuration,
1390 EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
1391
1392 /* Wait for all RX packets to drain out of MTL */
1393 for (i = 0; i < 1000000; i++) {
1394 u32 val = readl(&eqos->mtl_regs->rxq0_debug);
1395 u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
1396 EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
1397 u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
1398 EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
1399 if ((!prxq) && (!rxqsts))
1400 break;
1401 }
1402
1403 /* Turn off RX DMA */
1404 clrbits_le32(&eqos->dma_regs->ch0_rx_control,
1405 EQOS_DMA_CH0_RX_CONTROL_SR);
1406
1407 if (eqos->phy) {
1408 phy_shutdown(eqos->phy);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001409 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001410 eqos->config->ops->eqos_stop_resets(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001411
1412 debug("%s: OK\n", __func__);
1413}
1414
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001415static int eqos_send(struct udevice *dev, void *packet, int length)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001416{
1417 struct eqos_priv *eqos = dev_get_priv(dev);
1418 struct eqos_desc *tx_desc;
1419 int i;
1420
1421 debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
1422 length);
1423
1424 memcpy(eqos->tx_dma_buf, packet, length);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001425 eqos->config->ops->eqos_flush_buffer(eqos->tx_dma_buf, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001426
Marek Vasut6f1e6682021-01-07 11:12:16 +01001427 tx_desc = eqos_get_desc(eqos, eqos->tx_desc_idx, false);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001428 eqos->tx_desc_idx++;
1429 eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
1430
1431 tx_desc->des0 = (ulong)eqos->tx_dma_buf;
1432 tx_desc->des1 = 0;
1433 tx_desc->des2 = length;
1434 /*
1435 * Make sure that if HW sees the _OWN write below, it will see all the
1436 * writes to the rest of the descriptor too.
1437 */
1438 mb();
1439 tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001440 eqos->config->ops->eqos_flush_desc(tx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001441
Marek Vasut6f1e6682021-01-07 11:12:16 +01001442 writel((ulong)eqos_get_desc(eqos, eqos->tx_desc_idx, false),
Marek Vasut83858d82020-03-23 02:03:50 +01001443 &eqos->dma_regs->ch0_txdesc_tail_pointer);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001444
1445 for (i = 0; i < 1000000; i++) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001446 eqos->config->ops->eqos_inval_desc(tx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001447 if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN))
1448 return 0;
1449 udelay(1);
1450 }
1451
1452 debug("%s: TX timeout\n", __func__);
1453
1454 return -ETIMEDOUT;
1455}
1456
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001457static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001458{
1459 struct eqos_priv *eqos = dev_get_priv(dev);
1460 struct eqos_desc *rx_desc;
1461 int length;
1462
1463 debug("%s(dev=%p, flags=%x):\n", __func__, dev, flags);
1464
Marek Vasut6f1e6682021-01-07 11:12:16 +01001465 rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
Marek Vasut738ee272020-03-23 02:09:21 +01001466 eqos->config->ops->eqos_inval_desc(rx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001467 if (rx_desc->des3 & EQOS_DESC3_OWN) {
1468 debug("%s: RX packet not available\n", __func__);
1469 return -EAGAIN;
1470 }
1471
1472 *packetp = eqos->rx_dma_buf +
1473 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1474 length = rx_desc->des3 & 0x7fff;
1475 debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
1476
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001477 eqos->config->ops->eqos_inval_buffer(*packetp, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001478
1479 return length;
1480}
1481
Patrick Delaunay50d86e52019-08-01 11:29:02 +02001482static int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001483{
1484 struct eqos_priv *eqos = dev_get_priv(dev);
1485 uchar *packet_expected;
1486 struct eqos_desc *rx_desc;
1487
1488 debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
1489
1490 packet_expected = eqos->rx_dma_buf +
1491 (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
1492 if (packet != packet_expected) {
1493 debug("%s: Unexpected packet (expected %p)\n", __func__,
1494 packet_expected);
1495 return -EINVAL;
1496 }
1497
Fugang Duan3a97da12020-05-03 22:41:17 +08001498 eqos->config->ops->eqos_inval_buffer(packet, length);
1499
Marek Vasut6f1e6682021-01-07 11:12:16 +01001500 rx_desc = eqos_get_desc(eqos, eqos->rx_desc_idx, true);
Marek Vasuta83ca0c2020-03-23 02:09:55 +01001501
Marek Vasut24891dd2020-03-23 02:11:46 +01001502 rx_desc->des0 = 0;
1503 mb();
1504 eqos->config->ops->eqos_flush_desc(rx_desc);
Marek Vasuta83ca0c2020-03-23 02:09:55 +01001505 eqos->config->ops->eqos_inval_buffer(packet, length);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001506 rx_desc->des0 = (u32)(ulong)packet;
1507 rx_desc->des1 = 0;
1508 rx_desc->des2 = 0;
1509 /*
1510 * Make sure that if HW sees the _OWN write below, it will see all the
1511 * writes to the rest of the descriptor too.
1512 */
1513 mb();
Marek Vasut4332d802020-03-23 02:02:57 +01001514 rx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001515 eqos->config->ops->eqos_flush_desc(rx_desc);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001516
1517 writel((ulong)rx_desc, &eqos->dma_regs->ch0_rxdesc_tail_pointer);
1518
1519 eqos->rx_desc_idx++;
1520 eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
1521
1522 return 0;
1523}
1524
1525static int eqos_probe_resources_core(struct udevice *dev)
1526{
1527 struct eqos_priv *eqos = dev_get_priv(dev);
1528 int ret;
1529
1530 debug("%s(dev=%p):\n", __func__, dev);
1531
Marek Vasut6f1e6682021-01-07 11:12:16 +01001532 eqos->descs = eqos_alloc_descs(eqos, EQOS_DESCRIPTORS_NUM);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001533 if (!eqos->descs) {
1534 debug("%s: eqos_alloc_descs() failed\n", __func__);
1535 ret = -ENOMEM;
1536 goto err;
1537 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001538
1539 eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
1540 if (!eqos->tx_dma_buf) {
1541 debug("%s: memalign(tx_dma_buf) failed\n", __func__);
1542 ret = -ENOMEM;
1543 goto err_free_descs;
1544 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001545 debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001546
1547 eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
1548 if (!eqos->rx_dma_buf) {
1549 debug("%s: memalign(rx_dma_buf) failed\n", __func__);
1550 ret = -ENOMEM;
1551 goto err_free_tx_dma_buf;
1552 }
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001553 debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001554
1555 eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
1556 if (!eqos->rx_pkt) {
1557 debug("%s: malloc(rx_pkt) failed\n", __func__);
1558 ret = -ENOMEM;
1559 goto err_free_rx_dma_buf;
1560 }
1561 debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
1562
Marek Vasuta83ca0c2020-03-23 02:09:55 +01001563 eqos->config->ops->eqos_inval_buffer(eqos->rx_dma_buf,
1564 EQOS_MAX_PACKET_SIZE * EQOS_DESCRIPTORS_RX);
1565
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001566 debug("%s: OK\n", __func__);
1567 return 0;
1568
1569err_free_rx_dma_buf:
1570 free(eqos->rx_dma_buf);
1571err_free_tx_dma_buf:
1572 free(eqos->tx_dma_buf);
1573err_free_descs:
1574 eqos_free_descs(eqos->descs);
1575err:
1576
1577 debug("%s: returns %d\n", __func__, ret);
1578 return ret;
1579}
1580
1581static int eqos_remove_resources_core(struct udevice *dev)
1582{
1583 struct eqos_priv *eqos = dev_get_priv(dev);
1584
1585 debug("%s(dev=%p):\n", __func__, dev);
1586
1587 free(eqos->rx_pkt);
1588 free(eqos->rx_dma_buf);
1589 free(eqos->tx_dma_buf);
1590 eqos_free_descs(eqos->descs);
1591
1592 debug("%s: OK\n", __func__);
1593 return 0;
1594}
1595
1596static int eqos_probe_resources_tegra186(struct udevice *dev)
1597{
1598 struct eqos_priv *eqos = dev_get_priv(dev);
1599 int ret;
1600
1601 debug("%s(dev=%p):\n", __func__, dev);
1602
1603 ret = reset_get_by_name(dev, "eqos", &eqos->reset_ctl);
1604 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001605 pr_err("reset_get_by_name(rst) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001606 return ret;
1607 }
1608
1609 ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
1610 &eqos->phy_reset_gpio,
1611 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
1612 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001613 pr_err("gpio_request_by_name(phy reset) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001614 goto err_free_reset_eqos;
1615 }
1616
1617 ret = clk_get_by_name(dev, "slave_bus", &eqos->clk_slave_bus);
1618 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001619 pr_err("clk_get_by_name(slave_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001620 goto err_free_gpio_phy_reset;
1621 }
1622
1623 ret = clk_get_by_name(dev, "master_bus", &eqos->clk_master_bus);
1624 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001625 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001626 goto err_free_clk_slave_bus;
1627 }
1628
1629 ret = clk_get_by_name(dev, "rx", &eqos->clk_rx);
1630 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001631 pr_err("clk_get_by_name(rx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001632 goto err_free_clk_master_bus;
1633 }
1634
1635 ret = clk_get_by_name(dev, "ptp_ref", &eqos->clk_ptp_ref);
1636 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001637 pr_err("clk_get_by_name(ptp_ref) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001638 goto err_free_clk_rx;
1639 return ret;
1640 }
1641
1642 ret = clk_get_by_name(dev, "tx", &eqos->clk_tx);
1643 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001644 pr_err("clk_get_by_name(tx) failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001645 goto err_free_clk_ptp_ref;
1646 }
1647
1648 debug("%s: OK\n", __func__);
1649 return 0;
1650
1651err_free_clk_ptp_ref:
1652 clk_free(&eqos->clk_ptp_ref);
1653err_free_clk_rx:
1654 clk_free(&eqos->clk_rx);
1655err_free_clk_master_bus:
1656 clk_free(&eqos->clk_master_bus);
1657err_free_clk_slave_bus:
1658 clk_free(&eqos->clk_slave_bus);
1659err_free_gpio_phy_reset:
1660 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1661err_free_reset_eqos:
1662 reset_free(&eqos->reset_ctl);
1663
1664 debug("%s: returns %d\n", __func__, ret);
1665 return ret;
1666}
1667
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001668/* board-specific Ethernet Interface initializations. */
Patrick Delaunay53e3d522019-08-01 11:29:03 +02001669__weak int board_interface_eth_init(struct udevice *dev,
1670 phy_interface_t interface_type)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001671{
1672 return 0;
1673}
1674
1675static int eqos_probe_resources_stm32(struct udevice *dev)
1676{
1677 struct eqos_priv *eqos = dev_get_priv(dev);
1678 int ret;
1679 phy_interface_t interface;
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001680
1681 debug("%s(dev=%p):\n", __func__, dev);
1682
1683 interface = eqos->config->interface(dev);
1684
Marek BehĂșnffb0f6f2022-04-07 00:33:03 +02001685 if (interface == PHY_INTERFACE_MODE_NA) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001686 pr_err("Invalid PHY interface\n");
1687 return -EINVAL;
1688 }
1689
Patrick Delaunay53e3d522019-08-01 11:29:03 +02001690 ret = board_interface_eth_init(dev, interface);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001691 if (ret)
1692 return -EINVAL;
1693
Patrick Delaunay4f60a512020-03-18 10:50:16 +01001694 eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
1695
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001696 ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
1697 if (ret) {
1698 pr_err("clk_get_by_name(master_bus) failed: %d", ret);
1699 goto err_probe;
1700 }
1701
1702 ret = clk_get_by_name(dev, "mac-clk-rx", &eqos->clk_rx);
1703 if (ret) {
1704 pr_err("clk_get_by_name(rx) failed: %d", ret);
1705 goto err_free_clk_master_bus;
1706 }
1707
1708 ret = clk_get_by_name(dev, "mac-clk-tx", &eqos->clk_tx);
1709 if (ret) {
1710 pr_err("clk_get_by_name(tx) failed: %d", ret);
1711 goto err_free_clk_rx;
1712 }
1713
1714 /* Get ETH_CLK clocks (optional) */
1715 ret = clk_get_by_name(dev, "eth-ck", &eqos->clk_ck);
1716 if (ret)
1717 pr_warn("No phy clock provided %d", ret);
1718
1719 debug("%s: OK\n", __func__);
1720 return 0;
1721
1722err_free_clk_rx:
1723 clk_free(&eqos->clk_rx);
1724err_free_clk_master_bus:
1725 clk_free(&eqos->clk_master_bus);
1726err_probe:
1727
1728 debug("%s: returns %d\n", __func__, ret);
1729 return ret;
1730}
1731
Marek BehĂșn123ca112022-04-07 00:33:01 +02001732static phy_interface_t eqos_get_interface_tegra186(const struct udevice *dev)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001733{
1734 return PHY_INTERFACE_MODE_MII;
1735}
1736
Fugang Duan3a97da12020-05-03 22:41:17 +08001737static int eqos_probe_resources_imx(struct udevice *dev)
1738{
1739 struct eqos_priv *eqos = dev_get_priv(dev);
1740 phy_interface_t interface;
1741
1742 debug("%s(dev=%p):\n", __func__, dev);
1743
1744 interface = eqos->config->interface(dev);
1745
Marek BehĂșnffb0f6f2022-04-07 00:33:03 +02001746 if (interface == PHY_INTERFACE_MODE_NA) {
Fugang Duan3a97da12020-05-03 22:41:17 +08001747 pr_err("Invalid PHY interface\n");
1748 return -EINVAL;
1749 }
1750
1751 debug("%s: OK\n", __func__);
1752 return 0;
1753}
1754
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001755static int eqos_remove_resources_tegra186(struct udevice *dev)
1756{
1757 struct eqos_priv *eqos = dev_get_priv(dev);
1758
1759 debug("%s(dev=%p):\n", __func__, dev);
1760
Fugang Duan3a97da12020-05-03 22:41:17 +08001761#ifdef CONFIG_CLK
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001762 clk_free(&eqos->clk_tx);
1763 clk_free(&eqos->clk_ptp_ref);
1764 clk_free(&eqos->clk_rx);
1765 clk_free(&eqos->clk_slave_bus);
1766 clk_free(&eqos->clk_master_bus);
Fugang Duan3a97da12020-05-03 22:41:17 +08001767#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001768 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1769 reset_free(&eqos->reset_ctl);
1770
1771 debug("%s: OK\n", __func__);
1772 return 0;
1773}
1774
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001775static int eqos_remove_resources_stm32(struct udevice *dev)
1776{
Fugang Duan3a97da12020-05-03 22:41:17 +08001777#ifdef CONFIG_CLK
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001778 struct eqos_priv *eqos = dev_get_priv(dev);
1779
1780 debug("%s(dev=%p):\n", __func__, dev);
1781
1782 clk_free(&eqos->clk_tx);
1783 clk_free(&eqos->clk_rx);
1784 clk_free(&eqos->clk_master_bus);
1785 if (clk_valid(&eqos->clk_ck))
1786 clk_free(&eqos->clk_ck);
Fugang Duan3a97da12020-05-03 22:41:17 +08001787#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001788
Christophe Roullier5177b312020-03-18 10:50:15 +01001789 if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
1790 dm_gpio_free(dev, &eqos->phy_reset_gpio);
1791
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001792 debug("%s: OK\n", __func__);
1793 return 0;
1794}
1795
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001796static int eqos_probe(struct udevice *dev)
1797{
1798 struct eqos_priv *eqos = dev_get_priv(dev);
1799 int ret;
1800
1801 debug("%s(dev=%p):\n", __func__, dev);
1802
1803 eqos->dev = dev;
1804 eqos->config = (void *)dev_get_driver_data(dev);
1805
Masahiro Yamada25484932020-07-17 14:36:48 +09001806 eqos->regs = dev_read_addr(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001807 if (eqos->regs == FDT_ADDR_T_NONE) {
Masahiro Yamada25484932020-07-17 14:36:48 +09001808 pr_err("dev_read_addr() failed");
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001809 return -ENODEV;
1810 }
1811 eqos->mac_regs = (void *)(eqos->regs + EQOS_MAC_REGS_BASE);
1812 eqos->mtl_regs = (void *)(eqos->regs + EQOS_MTL_REGS_BASE);
1813 eqos->dma_regs = (void *)(eqos->regs + EQOS_DMA_REGS_BASE);
1814 eqos->tegra186_regs = (void *)(eqos->regs + EQOS_TEGRA186_REGS_BASE);
1815
1816 ret = eqos_probe_resources_core(dev);
1817 if (ret < 0) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +09001818 pr_err("eqos_probe_resources_core() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001819 return ret;
1820 }
1821
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001822 ret = eqos->config->ops->eqos_probe_resources(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001823 if (ret < 0) {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001824 pr_err("eqos_probe_resources() failed: %d", ret);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001825 goto err_remove_resources_core;
1826 }
1827
Marek Vasut3fbd17a2021-11-13 03:23:52 +01001828 ret = eqos->config->ops->eqos_start_clks(dev);
1829 if (ret < 0) {
1830 pr_err("eqos_start_clks() failed: %d", ret);
1831 goto err_remove_resources_tegra;
1832 }
1833
Ye Li6a895d02020-05-03 22:41:15 +08001834#ifdef CONFIG_DM_ETH_PHY
1835 eqos->mii = eth_phy_get_mdio_bus(dev);
1836#endif
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001837 if (!eqos->mii) {
Ye Li6a895d02020-05-03 22:41:15 +08001838 eqos->mii = mdio_alloc();
1839 if (!eqos->mii) {
1840 pr_err("mdio_alloc() failed");
1841 ret = -ENOMEM;
Marek Vasut3fbd17a2021-11-13 03:23:52 +01001842 goto err_stop_clks;
Ye Li6a895d02020-05-03 22:41:15 +08001843 }
1844 eqos->mii->read = eqos_mdio_read;
1845 eqos->mii->write = eqos_mdio_write;
1846 eqos->mii->priv = eqos;
1847 strcpy(eqos->mii->name, dev->name);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001848
Ye Li6a895d02020-05-03 22:41:15 +08001849 ret = mdio_register(eqos->mii);
1850 if (ret < 0) {
1851 pr_err("mdio_register() failed: %d", ret);
1852 goto err_free_mdio;
1853 }
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001854 }
1855
Ye Li6a895d02020-05-03 22:41:15 +08001856#ifdef CONFIG_DM_ETH_PHY
1857 eth_phy_set_mdio_bus(dev, eqos->mii);
1858#endif
1859
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001860 debug("%s: OK\n", __func__);
1861 return 0;
1862
1863err_free_mdio:
1864 mdio_free(eqos->mii);
Marek Vasut3fbd17a2021-11-13 03:23:52 +01001865err_stop_clks:
1866 eqos->config->ops->eqos_stop_clks(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001867err_remove_resources_tegra:
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001868 eqos->config->ops->eqos_remove_resources(dev);
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001869err_remove_resources_core:
1870 eqos_remove_resources_core(dev);
1871
1872 debug("%s: returns %d\n", __func__, ret);
1873 return ret;
1874}
1875
1876static int eqos_remove(struct udevice *dev)
1877{
1878 struct eqos_priv *eqos = dev_get_priv(dev);
1879
1880 debug("%s(dev=%p):\n", __func__, dev);
1881
1882 mdio_unregister(eqos->mii);
1883 mdio_free(eqos->mii);
Marek Vasut3fbd17a2021-11-13 03:23:52 +01001884 eqos->config->ops->eqos_stop_clks(dev);
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001885 eqos->config->ops->eqos_remove_resources(dev);
1886
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001887 eqos_probe_resources_core(dev);
1888
1889 debug("%s: OK\n", __func__);
1890 return 0;
1891}
1892
Patrick Delaunayc6a0df22021-07-20 20:09:56 +02001893static int eqos_null_ops(struct udevice *dev)
1894{
1895 return 0;
1896}
1897
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001898static const struct eth_ops eqos_ops = {
1899 .start = eqos_start,
1900 .stop = eqos_stop,
1901 .send = eqos_send,
1902 .recv = eqos_recv,
1903 .free_pkt = eqos_free_pkt,
1904 .write_hwaddr = eqos_write_hwaddr,
Ye Li580fab42020-05-03 22:41:20 +08001905 .read_rom_hwaddr = eqos_read_rom_hwaddr,
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001906};
1907
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001908static struct eqos_ops eqos_tegra186_ops = {
Marek Vasut6f1e6682021-01-07 11:12:16 +01001909 .eqos_inval_desc = eqos_inval_desc_generic,
1910 .eqos_flush_desc = eqos_flush_desc_generic,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001911 .eqos_inval_buffer = eqos_inval_buffer_tegra186,
1912 .eqos_flush_buffer = eqos_flush_buffer_tegra186,
1913 .eqos_probe_resources = eqos_probe_resources_tegra186,
1914 .eqos_remove_resources = eqos_remove_resources_tegra186,
1915 .eqos_stop_resets = eqos_stop_resets_tegra186,
1916 .eqos_start_resets = eqos_start_resets_tegra186,
1917 .eqos_stop_clks = eqos_stop_clks_tegra186,
1918 .eqos_start_clks = eqos_start_clks_tegra186,
1919 .eqos_calibrate_pads = eqos_calibrate_pads_tegra186,
1920 .eqos_disable_calibration = eqos_disable_calibration_tegra186,
1921 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_tegra186,
1922 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_tegra186
1923};
1924
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02001925static const struct eqos_config __maybe_unused eqos_tegra186_config = {
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001926 .reg_access_always_ok = false,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001927 .mdio_wait = 10,
1928 .swr_wait = 10,
1929 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1930 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_20_35,
Marek Vasut6f1e6682021-01-07 11:12:16 +01001931 .axi_bus_width = EQOS_AXI_WIDTH_128,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001932 .interface = eqos_get_interface_tegra186,
1933 .ops = &eqos_tegra186_ops
1934};
1935
1936static struct eqos_ops eqos_stm32_ops = {
Fugang Duan3a97da12020-05-03 22:41:17 +08001937 .eqos_inval_desc = eqos_inval_desc_generic,
1938 .eqos_flush_desc = eqos_flush_desc_generic,
1939 .eqos_inval_buffer = eqos_inval_buffer_generic,
1940 .eqos_flush_buffer = eqos_flush_buffer_generic,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001941 .eqos_probe_resources = eqos_probe_resources_stm32,
1942 .eqos_remove_resources = eqos_remove_resources_stm32,
Patrick Delaunayc6a0df22021-07-20 20:09:56 +02001943 .eqos_stop_resets = eqos_null_ops,
1944 .eqos_start_resets = eqos_null_ops,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001945 .eqos_stop_clks = eqos_stop_clks_stm32,
1946 .eqos_start_clks = eqos_start_clks_stm32,
Patrick Delaunayc6a0df22021-07-20 20:09:56 +02001947 .eqos_calibrate_pads = eqos_null_ops,
1948 .eqos_disable_calibration = eqos_null_ops,
1949 .eqos_set_tx_clk_speed = eqos_null_ops,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001950 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_stm32
1951};
1952
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02001953static const struct eqos_config __maybe_unused eqos_stm32_config = {
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001954 .reg_access_always_ok = false,
1955 .mdio_wait = 10000,
1956 .swr_wait = 50,
1957 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_AV,
1958 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
Marek Vasut6f1e6682021-01-07 11:12:16 +01001959 .axi_bus_width = EQOS_AXI_WIDTH_64,
Marek BehĂșn123ca112022-04-07 00:33:01 +02001960 .interface = dev_read_phy_mode,
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02001961 .ops = &eqos_stm32_ops
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001962};
1963
Fugang Duan3a97da12020-05-03 22:41:17 +08001964static struct eqos_ops eqos_imx_ops = {
1965 .eqos_inval_desc = eqos_inval_desc_generic,
1966 .eqos_flush_desc = eqos_flush_desc_generic,
1967 .eqos_inval_buffer = eqos_inval_buffer_generic,
1968 .eqos_flush_buffer = eqos_flush_buffer_generic,
1969 .eqos_probe_resources = eqos_probe_resources_imx,
Patrick Delaunayc6a0df22021-07-20 20:09:56 +02001970 .eqos_remove_resources = eqos_null_ops,
1971 .eqos_stop_resets = eqos_null_ops,
1972 .eqos_start_resets = eqos_null_ops,
1973 .eqos_stop_clks = eqos_null_ops,
1974 .eqos_start_clks = eqos_null_ops,
1975 .eqos_calibrate_pads = eqos_null_ops,
1976 .eqos_disable_calibration = eqos_null_ops,
Fugang Duan3a97da12020-05-03 22:41:17 +08001977 .eqos_set_tx_clk_speed = eqos_set_tx_clk_speed_imx,
1978 .eqos_get_tick_clk_rate = eqos_get_tick_clk_rate_imx
1979};
1980
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02001981struct eqos_config __maybe_unused eqos_imx_config = {
Fugang Duan3a97da12020-05-03 22:41:17 +08001982 .reg_access_always_ok = false,
Ye Li440b28a2020-12-28 20:15:10 +08001983 .mdio_wait = 10,
Fugang Duan3a97da12020-05-03 22:41:17 +08001984 .swr_wait = 50,
1985 .config_mac = EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB,
1986 .config_mac_mdio = EQOS_MAC_MDIO_ADDRESS_CR_250_300,
Marek Vasut6f1e6682021-01-07 11:12:16 +01001987 .axi_bus_width = EQOS_AXI_WIDTH_64,
Marek BehĂșn123ca112022-04-07 00:33:01 +02001988 .interface = dev_read_phy_mode,
Fugang Duan3a97da12020-05-03 22:41:17 +08001989 .ops = &eqos_imx_ops
1990};
1991
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001992static const struct udevice_id eqos_ids[] = {
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02001993#if IS_ENABLED(CONFIG_DWC_ETH_QOS_TEGRA186)
Stephen Warrenba4dfef2016-10-21 14:46:47 -06001994 {
1995 .compatible = "nvidia,tegra186-eqos",
1996 .data = (ulong)&eqos_tegra186_config
1997 },
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02001998#endif
1999#if IS_ENABLED(CONFIG_DWC_ETH_QOS_STM32)
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002000 {
Patrick Delaunaya718a5d2020-05-14 15:00:23 +02002001 .compatible = "st,stm32mp1-dwmac",
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002002 .data = (ulong)&eqos_stm32_config
2003 },
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002004#endif
2005#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX)
Fugang Duan3a97da12020-05-03 22:41:17 +08002006 {
Marek Vasut3fa3f232022-02-26 04:36:37 +01002007 .compatible = "nxp,imx8mp-dwmac-eqos",
Fugang Duan3a97da12020-05-03 22:41:17 +08002008 .data = (ulong)&eqos_imx_config
2009 },
Patrick Delaunaya08f2f72020-06-08 11:27:19 +02002010#endif
Christophe Roullierac2d4ef2019-05-17 15:08:44 +02002011
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002012 { }
2013};
2014
2015U_BOOT_DRIVER(eth_eqos) = {
2016 .name = "eth_eqos",
2017 .id = UCLASS_ETH,
Fugang Duan3a97da12020-05-03 22:41:17 +08002018 .of_match = of_match_ptr(eqos_ids),
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002019 .probe = eqos_probe,
2020 .remove = eqos_remove,
2021 .ops = &eqos_ops,
Simon Glass41575d82020-12-03 16:55:17 -07002022 .priv_auto = sizeof(struct eqos_priv),
Simon Glasscaa4daa2020-12-03 16:55:18 -07002023 .plat_auto = sizeof(struct eth_pdata),
Stephen Warrenba4dfef2016-10-21 14:46:47 -06002024};