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gerrit.cesnet.cz / github / trini / u-boot / aadb72503cd1602349a5fe53356d5f55ecc1b900 / . / board / kup / kup4k / s1d13706.h
blob: cd5eccc6f583d178e766a580fd4555cf017c8cb6 [file] [log] [blame]
wdenk0608e042004-03-25 19:29:38 +0000[diff] [blame]1/*---------------------------------------------------------------------------- */
2/* */
3/* File generated by S1D13706CFG.EXE */
4/* */
5/* Copyright (c) 2000,2001 Epson Research and Development, Inc. */
6/* All rights reserved. */
7/* */
8/*---------------------------------------------------------------------------- */
9
10/* Panel: 320x240x8bpp 70Hz Color Single STN 8-bit (PCLK=6.250MHz) (Format 2) */
11
12#define S1D_DISPLAY_WIDTH 320
13#define S1D_DISPLAY_HEIGHT 240
14#define S1D_DISPLAY_BPP 8
15#define S1D_DISPLAY_SCANLINE_BYTES 320
16#define S1D_PHYSICAL_VMEM_ADDR 0x800A0000L
17#define S1D_PHYSICAL_VMEM_SIZE 0x14000L
18#define S1D_PHYSICAL_REG_ADDR 0x80080000L
19#define S1D_PHYSICAL_REG_SIZE 0x100
20#define S1D_DISPLAY_PCLK 6250
21#define S1D_PALETTE_SIZE 256
22#define S1D_REGDELAYOFF 0xFFFE
23#define S1D_REGDELAYON 0xFFFF
24
25#define S1D_WRITE_PALETTE(p,i,r,g,b) \
26{ \
27 ((volatile S1D_VALUE*)(p))[0x0A/sizeof(S1D_VALUE)] = (S1D_VALUE)((r)>>4); \
28 ((volatile S1D_VALUE*)(p))[0x09/sizeof(S1D_VALUE)] = (S1D_VALUE)((g)>>4); \
29 ((volatile S1D_VALUE*)(p))[0x08/sizeof(S1D_VALUE)] = (S1D_VALUE)((b)>>4); \
30 ((volatile S1D_VALUE*)(p))[0x0B/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
31}
32
33#define S1D_READ_PALETTE(p,i,r,g,b) \
34{ \
35 ((volatile S1D_VALUE*)(p))[0x0F/sizeof(S1D_VALUE)] = (S1D_VALUE)(i); \
36 r = ((volatile S1D_VALUE*)(p))[0x0E/sizeof(S1D_VALUE)]; \
37 g = ((volatile S1D_VALUE*)(p))[0x0D/sizeof(S1D_VALUE)]; \
38 b = ((volatile S1D_VALUE*)(p))[0x0C/sizeof(S1D_VALUE)]; \
39}
40
41typedef unsigned short S1D_INDEX;
42typedef unsigned char S1D_VALUE;
43
44
45typedef struct
46{
47 S1D_INDEX Index;
48 S1D_VALUE Value;
49} S1D_REGS;
50
51
52static S1D_REGS aS1DRegs_prelimn[] =
53{
54 {0x10,0x00}, /* PANEL Type Register */
55 {0xA8,0x00}, /* GPIO Config Register 0 */
56 {0xA9,0x80}, /* GPIO Config Register 1 */
57
58};
59
60static S1D_REGS aS1DRegs_stn[] =
61{
62 {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
63 {0x10,0xD0}, /* PANEL Type Register */
64 {0x11,0x00}, /* MOD Rate Register */
65 {0x14,0x27}, /* Horizontal Display Period Register */
66 {0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
67 {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
68 {0x18,0xF0}, /* Vertical Total Register 0 */
69 {0x19,0x00}, /* Vertical Total Register 1 */
70 {0x1C,0xEF}, /* Vertical Display Period Register 0 */
71 {0x1D,0x00}, /* Vertical Display Period Register 1 */
72 {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
73 {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
74 {0x20,0x87}, /* Horizontal Sync Pulse Width Register */
75 {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
76 {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
77 {0x24,0x80}, /* Vertical Sync Pulse Width Register */
78 {0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
79 {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
80 {0x70,0x83}, /* Display Mode Register */
81 {0x71,0x00}, /* Special Effects Register */
82 {0x74,0x00}, /* Main Window Display Start Address Register 0 */
83 {0x75,0x00}, /* Main Window Display Start Address Register 1 */
84 {0x76,0x00}, /* Main Window Display Start Address Register 2 */
85 {0x78,0x50}, /* Main Window Address Offset Register 0 */
86 {0x79,0x00}, /* Main Window Address Offset Register 1 */
87 {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
88 {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
89 {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
90 {0x80,0x50}, /* Sub Window Address Offset Register 0 */
91 {0x81,0x00}, /* Sub Window Address Offset Register 1 */
92 {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
93 {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
94 {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
95 {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
96 {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
97 {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
98 {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
99 {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
100 {0xA0,0x00}, /* Power Save Config Register */
101 {0xA1,0x00}, /* CPU Access Control Register */
102 {0xA2,0x00}, /* Software Reset Register */
103 {0xA3,0x00}, /* BIG Endian Support Register */
104 {0xA4,0x00}, /* Scratch Pad Register 0 */
105 {0xA5,0x00}, /* Scratch Pad Register 1 */
106 {0xA8,0x01}, /* GPIO Config Register 0 */
107 {0xA9,0x80}, /* GPIO Config Register 1 */
108 {0xAC,0x01}, /* GPIO Status Control Register 0 */
109 {0xAD,0x00}, /* GPIO Status Control Register 1 */
110 {0xB0,0x10}, /* PWM CV Clock Control Register */
111 {0xB1,0x80}, /* PWM CV Clock Config Register */
112 {0xB2,0x00}, /* CV Clock Burst Length Register */
113 {0xAD,0x80}, /* reset seq */
114 {0x70,0x03},
115};
116
117static S1D_REGS aS1DRegs_tft[] =
118{
119 {0x04,0x10}, /* BUSCLK MEMCLK Config Register */
120 {0x05,0x42}, /* PCLK Config Register */
121 {0x10,0x61}, /* PANEL Type Register */
122 {0x11,0x00}, /* MOD Rate Register */
123 {0x12,0x30}, /* Horizontal Total Register */
124 {0x14,0x27}, /* Horizontal Display Period Register */
125 {0x16,0x11}, /* Horizontal Display Period Start Pos Register 0 */
126 {0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
127 {0x18,0xFA}, /* Vertical Total Register 0 */
128 {0x19,0x00}, /* Vertical Total Register 1 */
129 {0x1C,0xEF}, /* Vertical Display Period Register 0 */
130 {0x1D,0x00}, /* Vertical Display Period Register 1 */
131 {0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
132 {0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
133 {0x20,0x07}, /* Horizontal Sync Pulse Width Register */
134 {0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
135 {0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
136 {0x24,0x00}, /* Vertical Sync Pulse Width Register */
137 {0x26,0x00}, /* Vertical Sync Pulse Start Pos Register 0 */
138 {0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
139 {0x70,0x03}, /* Display Mode Register */
140 {0x71,0x00}, /* Special Effects Register */
141 {0x74,0x00}, /* Main Window Display Start Address Register 0 */
142 {0x75,0x00}, /* Main Window Display Start Address Register 1 */
143 {0x76,0x00}, /* Main Window Display Start Address Register 2 */
144 {0x78,0x50}, /* Main Window Address Offset Register 0 */
145 {0x79,0x00}, /* Main Window Address Offset Register 1 */
146 {0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
147 {0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
148 {0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
149 {0x80,0x50}, /* Sub Window Address Offset Register 0 */
150 {0x81,0x00}, /* Sub Window Address Offset Register 1 */
151 {0x84,0x00}, /* Sub Window X Start Pos Register 0 */
152 {0x85,0x00}, /* Sub Window X Start Pos Register 1 */
153 {0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
154 {0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
155 {0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
156 {0x8D,0x00}, /* Sub Window X End Pos Register 1 */
157 {0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
158 {0x91,0x00}, /* Sub Window Y End Pos Register 1 */
159 {0xA0,0x00}, /* Power Save Config Register */
160 {0xA1,0x00}, /* CPU Access Control Register */
161 {0xA2,0x00}, /* Software Reset Register */
162 {0xA3,0x00}, /* BIG Endian Support Register */
163 {0xA4,0x00}, /* Scratch Pad Register 0 */
164 {0xA5,0x00}, /* Scratch Pad Register 1 */
165 {0xA8,0x01}, /* GPIO Config Register 0 */
166 {0xA9,0x80}, /* GPIO Config Register 1 */
167 {0xAC,0x01}, /* GPIO Status Control Register 0 */
168 {0xAD,0x00}, /* GPIO Status Control Register 1 */
169 {0xB0,0x10}, /* PWM CV Clock Control Register */
170 {0xB1,0x80}, /* PWM CV Clock Config Register */
171 {0xB2,0x00}, /* CV Clock Burst Length Register */
172 {0xAD,0x80}, /* reset seq */
173 {0x70,0x03},
174};