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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * (C) Copyright 2001-2004
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Stefan Roese98f4a3d2005-09-22 09:04:17 +02005 * (C) Copyright 2005
6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 *
Stefan Roese48a05a52006-02-07 16:51:04 +01008 * (C) Copyright 2006
9 * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
10 *
stroesea20b27a2004-12-16 18:05:42 +000011 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30/*
31 * board/config.h - configuration options, board specific
32 */
33
34#ifndef __CONFIG_H
35#define __CONFIG_H
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41
42#define CONFIG_405EP 1 /* This is a PPC405 CPU */
43#define CONFIG_4xx 1 /* ...member of PPC4xx family */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020044#define CONFIG_HH405 1 /* ...on a HH405 board */
stroesea20b27a2004-12-16 18:05:42 +000045
Wolfgang Denk2ae18242010-10-06 09:05:45 +020046#define CONFIG_SYS_TEXT_BASE 0xFFF80000
47
stroesea20b27a2004-12-16 18:05:42 +000048#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
49#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
50
51#define CONFIG_SYS_CLK_FREQ 33333400 /* external frequency to pll */
52
53#define CONFIG_BOARD_TYPES 1 /* support board types */
54
55#define CONFIG_BAUDRATE 9600
56#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
57
58#undef CONFIG_BOOTARGS
59#undef CONFIG_BOOTCOMMAND
60
61#define CONFIG_PREBOOT "autoupd"
62
Stefan Roese2c7b2ab2005-09-30 16:41:12 +020063#define CONFIG_EXTRA_ENV_SETTINGS \
64 "pciconfighost=1\0" \
65 ""
66
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
stroesea20b27a2004-12-16 18:05:42 +000068
Ben Warren96e21f82008-10-27 23:50:15 -070069#define CONFIG_PPC4xx_EMAC
Stefan Roese48a05a52006-02-07 16:51:04 +010070#define CONFIG_NET_MULTI 1
71#undef CONFIG_HAS_ETH1
72
stroesea20b27a2004-12-16 18:05:42 +000073#define CONFIG_MII 1 /* MII PHY management */
Stefan Roese48a05a52006-02-07 16:51:04 +010074#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000075#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
Stefan Roese48a05a52006-02-07 16:51:04 +010076#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
stroesea20b27a2004-12-16 18:05:42 +000077
78#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
79
Stefan Roese98f4a3d2005-09-22 09:04:17 +020080/*
81 * Video console
82 */
Stefan Roese2c7b2ab2005-09-30 16:41:12 +020083#define CONFIG_VIDEO /* for sm501 video support */
84
85#ifdef CONFIG_VIDEO
Stefan Roese98f4a3d2005-09-22 09:04:17 +020086#define CONFIG_VIDEO_SM501
87#if 0
88#define CONFIG_VIDEO_SM501_32BPP
89#else
90#define CONFIG_VIDEO_SM501_16BPP
91#endif
Stefan Roese48a05a52006-02-07 16:51:04 +010092#define CONFIG_VIDEO_SM501_FBMEM_OFFSET 0x10000
Stefan Roese98f4a3d2005-09-22 09:04:17 +020093#define CONFIG_CFB_CONSOLE
94#define CONFIG_VIDEO_LOGO
95#define CONFIG_VGA_AS_SINGLE_DEVICE
96#define CONFIG_CONSOLE_EXTRA_INFO
97#define CONFIG_VIDEO_SW_CURSOR
98#define CONFIG_SPLASH_SCREEN
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_CONSOLE_IS_IN_ENV
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200100#define CONFIG_SPLASH_SCREEN
101#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* for decompressed img */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200103
Stefan Roese2c7b2ab2005-09-30 16:41:12 +0200104#endif /* CONFIG_VIDEO */
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200105
Jon Loeliger11799432007-07-10 09:02:57 -0500106
107/*
108 * BOOTP options
109 */
110#define CONFIG_BOOTP_BOOTFILESIZE
111#define CONFIG_BOOTP_BOOTPATH
112#define CONFIG_BOOTP_GATEWAY
113#define CONFIG_BOOTP_HOSTNAME
114
115
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500116/*
117 * Command line configuration.
118 */
119#include <config_cmd_default.h>
120
121#define CONFIG_CMD_DHCP
122#define CONFIG_CMD_PCI
123#define CONFIG_CMD_IRQ
124#define CONFIG_CMD_IDE
125#define CONFIG_CMD_FAT
126#define CONFIG_CMD_EXT2
127#define CONFIG_CMD_ELF
128#define CONFIG_CMD_NAND
129#define CONFIG_CMD_I2C
130#define CONFIG_CMD_DATE
131#define CONFIG_CMD_MII
132#define CONFIG_CMD_PING
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500133#define CONFIG_CMD_EEPROM
134
Jon Loeliger11799432007-07-10 09:02:57 -0500135#ifdef CONFIG_VIDEO
136#define CONFIG_CMD_BMP
137#endif
stroesea20b27a2004-12-16 18:05:42 +0000138
139#define CONFIG_MAC_PARTITION
140#define CONFIG_DOS_PARTITION
141
142#define CONFIG_SUPPORT_VFAT
143
144#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */
145#undef CONFIG_AUTO_UPDATE_SHOW /* use board show routine */
146
stroesea20b27a2004-12-16 18:05:42 +0000147#undef CONFIG_BZIP2 /* include support for bzip2 compressed images */
148#undef CONFIG_WATCHDOG /* watchdog disabled */
149
150#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
151
152/*
153 * Miscellaneous configurable options
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_LONGHELP /* undef to save memory */
156#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
stroesea20b27a2004-12-16 18:05:42 +0000157
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
159#ifdef CONFIG_SYS_HUSH_PARSER
160#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
stroesea20b27a2004-12-16 18:05:42 +0000161#endif
162
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500163#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000165#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000167#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
169#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
170#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
stroesea20b27a2004-12-16 18:05:42 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
stroesea20b27a2004-12-16 18:05:42 +0000173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* print console @ startup */
stroesea20b27a2004-12-16 18:05:42 +0000175
176#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
179#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
stroesea20b27a2004-12-16 18:05:42 +0000180
Stefan Roese550650d2010-09-20 16:05:31 +0200181#define CONFIG_CONS_INDEX 2 /* Use UART1 */
182#define CONFIG_SYS_NS16550
183#define CONFIG_SYS_NS16550_SERIAL
184#define CONFIG_SYS_NS16550_REG_SIZE 1
185#define CONFIG_SYS_NS16550_CLK get_serial_clock()
186
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_BASE_BAUD 691200
stroesea20b27a2004-12-16 18:05:42 +0000189
190/* The following table includes the supported baudrates */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_BAUDRATE_TABLE \
stroesea20b27a2004-12-16 18:05:42 +0000192 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
193 57600, 115200, 230400, 460800, 921600 }
194
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
196#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
stroesea20b27a2004-12-16 18:05:42 +0000197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
stroesea20b27a2004-12-16 18:05:42 +0000199
200#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
201
202#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroesea20b27a2004-12-16 18:05:42 +0000205
206/*-----------------------------------------------------------------------
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200207 * RTC stuff
208 *-----------------------------------------------------------------------
209 */
210#define CONFIG_RTC_DS1338
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_SYS_I2C_RTC_ADDR 0x68
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200212
213/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000214 * NAND-FLASH stuff
215 *-----------------------------------------------------------------------
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200219#define NAND_BIG_DELAY_US 25
stroesea20b27a2004-12-16 18:05:42 +0000220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
222#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
223#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
224#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroesea20b27a2004-12-16 18:05:42 +0000225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
227#define CONFIG_SYS_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000228
229/*-----------------------------------------------------------------------
230 * PCI stuff
231 *-----------------------------------------------------------------------
232 */
233#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
234#define PCI_HOST_FORCE 1 /* configure as pci host */
235#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
236
237#define CONFIG_PCI /* include pci support */
238#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
239#define CONFIG_PCI_PNP /* do pci plug-and-play */
240 /* resource configuration */
241
242#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
243
244#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
247#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
248#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
249#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
250#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
251#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
252#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
253#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
254#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroesea20b27a2004-12-16 18:05:42 +0000255
256/*-----------------------------------------------------------------------
257 * IDE/ATA stuff
258 *-----------------------------------------------------------------------
259 */
260#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
261#undef CONFIG_IDE_LED /* no led for ide supported */
262#define CONFIG_IDE_RESET 1 /* reset for ide supported */
263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */
265#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
stroesea20b27a2004-12-16 18:05:42 +0000266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
268#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
stroesea20b27a2004-12-16 18:05:42 +0000269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
271#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
272#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
stroesea20b27a2004-12-16 18:05:42 +0000273
274/*
275 * For booting Linux, the board info and command line data
276 * have to be in the first 8 MB of memory, since this is
277 * the maximum mapped by the Linux kernel during initialization.
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
stroesea20b27a2004-12-16 18:05:42 +0000280/*-----------------------------------------------------------------------
281 * FLASH organization
282 */
283#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
284
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
286#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
stroesea20b27a2004-12-16 18:05:42 +0000287
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
289#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
stroesea20b27a2004-12-16 18:05:42 +0000290
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200291#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
292#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
293#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroesea20b27a2004-12-16 18:05:42 +0000294/*
295 * The following defines are added for buggy IOP480 byte interface.
296 * All other boards should use the standard values (CPCI405 etc.)
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
299#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
300#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
stroesea20b27a2004-12-16 18:05:42 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroesea20b27a2004-12-16 18:05:42 +0000303
304#if 0 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
306#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroesea20b27a2004-12-16 18:05:42 +0000307#endif
308
309/*-----------------------------------------------------------------------
310 * Start addresses for the final memory configuration
311 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
stroesea20b27a2004-12-16 18:05:42 +0000313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_SDRAM_BASE 0x00000000
315#define CONFIG_SYS_FLASH_BASE 0xFFF80000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200316#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
318#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 4 MB for malloc() */
stroesea20b27a2004-12-16 18:05:42 +0000319
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
321# define CONFIG_SYS_RAMBOOT 1
stroesea20b27a2004-12-16 18:05:42 +0000322#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323# undef CONFIG_SYS_RAMBOOT
stroesea20b27a2004-12-16 18:05:42 +0000324#endif
325
326/*-----------------------------------------------------------------------
327 * Environment Variable setup
328 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200329#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200330#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
331#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroesea20b27a2004-12-16 18:05:42 +0000332 /* total size of a CAT24WC16 is 2048 bytes */
333
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF4080000 /* NVRAM base address */
335#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
stroesea20b27a2004-12-16 18:05:42 +0000336
337/*-----------------------------------------------------------------------
338 * I2C EEPROM (CAT24WC16) for environment
339 */
340#define CONFIG_HARD_I2C /* I2c with hardware support */
Stefan Roesed0b0dca2010-04-01 14:37:24 +0200341#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
stroesea20b27a2004-12-16 18:05:42 +0000342#if 0 /* test-only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
stroesea20b27a2004-12-16 18:05:42 +0000344#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200345#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
stroesea20b27a2004-12-16 18:05:42 +0000346#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200347#define CONFIG_SYS_I2C_SLAVE 0x7F
stroesea20b27a2004-12-16 18:05:42 +0000348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT24WC08 */
350#define CONFIG_SYS_EEPROM_WREN 1
Stefan Roese98f4a3d2005-09-22 09:04:17 +0200351
stroesea20b27a2004-12-16 18:05:42 +0000352#if 1 /* test-only */
353/* CAT24WC08/16... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200354#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000355/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
357#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
stroesea20b27a2004-12-16 18:05:42 +0000358 /* 16 byte page write mode using*/
359 /* last 4 bits of the address */
360#else
361/* CAT24WC32/64... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
stroesea20b27a2004-12-16 18:05:42 +0000363/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
365#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
stroesea20b27a2004-12-16 18:05:42 +0000366 /* 32 byte page write mode using*/
367 /* last 5 bits of the address */
368#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroesea20b27a2004-12-16 18:05:42 +0000370
371/*-----------------------------------------------------------------------
stroesea20b27a2004-12-16 18:05:42 +0000372 * External Bus Controller (EBC) Setup
373 */
374
375#define CAN_BA 0xF0000000 /* CAN Base Address */
376#define LCD_BA 0xF1000000 /* Epson LCD Base Address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_NAND_BASE 0xF4000000 /* NAND FLASH Base Address */
378#define CONFIG_SYS_NVRAM_BASE 0xF4080000 /* NVRAM Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000379
380/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200381#define CONFIG_SYS_EBC_PB0AP 0x92015480
382#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000383
384/* Memory Bank 1 (Flash Bank 1, NAND-FLASH & NVRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_EBC_PB1AP 0x92015480
386#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000387
388/* Memory Bank 2 (8 Bit Peripheral: CAN, UART, RTC) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
390#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroesea20b27a2004-12-16 18:05:42 +0000391
392/* Memory Bank 3 (16 Bit Peripheral: FPGA internal, dig. IO) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200393#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
394#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000395
396/* Memory Bank 4 (Epson LCD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define CONFIG_SYS_EBC_PB4AP 0x03805380 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
398#define CONFIG_SYS_EBC_PB4CR LCD_BA | 0x7A000 /* BAS=0xF10,BS=8MB,BU=R/W,BW=16bit */
stroesea20b27a2004-12-16 18:05:42 +0000399
400/*-----------------------------------------------------------------------
401 * LCD Setup
402 */
403
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200404#define CONFIG_SYS_LCD_BIG_MEM 0xF1200000 /* Epson S1D13806 Mem Base Address */
405#define CONFIG_SYS_LCD_BIG_REG 0xF1000000 /* Epson S1D13806 Reg Base Address */
406#define CONFIG_SYS_LCD_SMALL_MEM 0xF1400000 /* Epson S1D13704 Mem Base Address */
407#define CONFIG_SYS_LCD_SMALL_REG 0xF140FFE0 /* Epson S1D13704 Reg Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000408
stroesea20b27a2004-12-16 18:05:42 +0000409/*-----------------------------------------------------------------------
410 * Universal Interrupt Controller (UIC) Setup
411 */
412
413/*
414 * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
415 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_UIC0_POLARITY (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
stroesea20b27a2004-12-16 18:05:42 +0000417
418/*-----------------------------------------------------------------------
419 * FPGA stuff
420 */
421
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200422#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0100100 /* FPGA internal Base Address */
stroesea20b27a2004-12-16 18:05:42 +0000423
stroesea20b27a2004-12-16 18:05:42 +0000424#define LCD_CLK_OFF 0x0000 /* Off */
425#define LCD_CLK_02083 0x1000 /* 2.083 MHz */
426#define LCD_CLK_03135 0x2000 /* 3.135 MHz */
427#define LCD_CLK_04165 0x3000 /* 4.165 MHz */
428#define LCD_CLK_06250 0x4000 /* 6.250 MHz */
429#define LCD_CLK_08330 0x5000 /* 8.330 MHz */
430#define LCD_CLK_12500 0x6000 /* 12.50 MHz */
431#define LCD_CLK_25000 0x7000 /* 25.00 MHz */
432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
434#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroesea20b27a2004-12-16 18:05:42 +0000435
436/* FPGA program pin configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200437#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
438#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
439#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
440#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
441#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroesea20b27a2004-12-16 18:05:42 +0000442
443/*-----------------------------------------------------------------------
444 * Definitions for initial stack pointer and data area (in data cache)
445 */
446/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200447#define CONFIG_SYS_TEMP_STACK_OCM 1
stroesea20b27a2004-12-16 18:05:42 +0000448
449/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200450#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
451#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
452#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200453#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
stroesea20b27a2004-12-16 18:05:42 +0000454
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200455#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
stroesea20b27a2004-12-16 18:05:42 +0000457
458/*-----------------------------------------------------------------------
459 * Definitions for GPIO setup (PPC405EP specific)
460 *
461 * GPIO0[0] - External Bus Controller BLAST output
462 * GPIO0[1-9] - Instruction trace outputs -> GPIO
463 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
464 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
465 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
466 * GPIO0[24-27] - UART0 control signal inputs/outputs
467 * GPIO0[28-29] - UART1 data signal input/output
468 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
469 */
Stefan Roeseafabb492010-09-12 06:21:37 +0200470#define CONFIG_SYS_GPIO0_OSRL 0x40000550
471#define CONFIG_SYS_GPIO0_OSRH 0x00000110
472#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
473#define CONFIG_SYS_GPIO0_ISR1H 0x15555440
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_GPIO0_TSRL 0x00000000
Stefan Roeseafabb492010-09-12 06:21:37 +0200475#define CONFIG_SYS_GPIO0_TSRH 0x00000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_GPIO0_TCR 0xF7FE0017
stroesea20b27a2004-12-16 18:05:42 +0000477
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200478#define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7)
479#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */
480#define CONFIG_SYS_TOUCH_RST (0x80000000 >> 9) /* GPIO9 */
481#define CONFIG_SYS_LCD0_RST (0x80000000 >> 30)
482#define CONFIG_SYS_LCD1_RST (0x80000000 >> 31)
stroesea20b27a2004-12-16 18:05:42 +0000483
484/*
stroesea20b27a2004-12-16 18:05:42 +0000485 * Default speed selection (cpu_plb_opb_ebc) in mhz.
486 * This value will be set if iic boot eprom is disabled.
487 */
488#if 0
489#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
490#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
491#endif
492#if 0
493#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
494#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
495#endif
496#if 1
497#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
498#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
499#endif
500
501#endif /* __CONFIG_H */