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Thomas Chouc960b132010-04-20 12:49:52 +08001/*
2 * Altera 10/100/1000 triple speed ethernet mac
3 *
4 * Copyright (C) 2008 Altera Corporation.
5 * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11#ifndef _ALTERA_TSE_H_
12#define _ALTERA_TSE_H_
13
Thomas Chou13146ec2015-11-06 09:36:41 +080014#define __packed_1_ __packed __aligned(1)
Thomas Chouc960b132010-04-20 12:49:52 +080015
Thomas Chou38fa4ac2015-11-09 11:02:15 +080016/* dma type */
17#define ALT_SGDMA 0
Thomas Choue3e87262015-11-09 14:36:29 +080018#define ALT_MSGDMA 1
Thomas Chou38fa4ac2015-11-09 11:02:15 +080019
Thomas Chouc960b132010-04-20 12:49:52 +080020/* SGDMA Stuff */
Thomas Chou4c8df1d2015-11-06 09:37:08 +080021#define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
Thomas Chouc960b132010-04-20 12:49:52 +080022
Thomas Chou4c8df1d2015-11-06 09:37:08 +080023#define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
24#define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
25#define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
Thomas Chouc960b132010-04-20 12:49:52 +080026
Thomas Chouc960b132010-04-20 12:49:52 +080027/*
28 * Descriptor control bit masks & offsets
29 *
30 * Note: The control byte physically occupies bits [31:24] in memory.
31 * The following bit-offsets are expressed relative to the LSB of
32 * the control register bitfield.
33 */
Thomas Chou4c8df1d2015-11-06 09:37:08 +080034#define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
35#define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
36#define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
37#define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
Thomas Chouc960b132010-04-20 12:49:52 +080038
39/*
40 * Descriptor status bit masks & offsets
41 *
42 * Note: The status byte physically occupies bits [23:16] in memory.
43 * The following bit-offsets are expressed relative to the LSB of
44 * the status register bitfield.
45 */
Thomas Chou4c8df1d2015-11-06 09:37:08 +080046#define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
Thomas Chouc960b132010-04-20 12:49:52 +080047
48/*
49 * The SGDMA controller buffer descriptor allocates
50 * 64 bits for each address. To support ANSI C, the
51 * struct implementing a descriptor places 32-bits
52 * of padding directly above each address; each pad must
53 * be cleared when initializing a descriptor.
54 */
55
56/*
57 * Buffer Descriptor data structure
58 *
59 */
60struct alt_sgdma_descriptor {
Thomas Chou2cd0a522015-11-06 09:36:26 +080061 u32 source; /* the address of data to be read. */
62 u32 source_pad;
Thomas Chouc960b132010-04-20 12:49:52 +080063
Thomas Chou2cd0a522015-11-06 09:36:26 +080064 u32 destination; /* the address to write data */
65 u32 destination_pad;
Thomas Chouc960b132010-04-20 12:49:52 +080066
Thomas Chou2cd0a522015-11-06 09:36:26 +080067 u32 next; /* the next descriptor in the list. */
68 u32 next_pad;
Thomas Chouc960b132010-04-20 12:49:52 +080069
Thomas Chou2cd0a522015-11-06 09:36:26 +080070 u16 bytes_to_transfer; /* the number of bytes to transfer */
71 u8 read_burst;
72 u8 write_burst;
Thomas Chouc960b132010-04-20 12:49:52 +080073
Thomas Chou2cd0a522015-11-06 09:36:26 +080074 u16 actual_bytes_transferred;/* bytes transferred by DMA */
75 u8 descriptor_status;
76 u8 descriptor_control;
Thomas Chouc960b132010-04-20 12:49:52 +080077
78} __packed_1_;
79
80/* SG-DMA Control/Status Slave registers map */
81
82struct alt_sgdma_registers {
Thomas Chou2cd0a522015-11-06 09:36:26 +080083 u32 status;
84 u32 status_pad[3];
85 u32 control;
86 u32 control_pad[3];
87 u32 next_descriptor_pointer;
88 u32 descriptor_pad[3];
Thomas Chouc960b132010-04-20 12:49:52 +080089};
90
Thomas Choue3e87262015-11-09 14:36:29 +080091/* mSGDMA Stuff */
92
93/* mSGDMA extended descriptor format */
94struct msgdma_extended_desc {
95 u32 read_addr_lo; /* data buffer source address low bits */
96 u32 write_addr_lo; /* data buffer destination address low bits */
97 u32 len;
98 u32 burst_seq_num;
99 u32 stride;
100 u32 read_addr_hi; /* data buffer source address high bits */
101 u32 write_addr_hi; /* data buffer destination address high bits */
102 u32 control; /* characteristics of the transfer */
103};
104
105/* mSGDMA descriptor control field bit definitions */
106#define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
107#define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
108#define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
109#define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
110#define MSGDMA_DESC_CTL_GO BIT(31)
111
112/* Tx buffer control flags */
113#define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
114 MSGDMA_DESC_CTL_GEN_EOP | \
115 MSGDMA_DESC_CTL_GO)
116
117#define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
118 MSGDMA_DESC_CTL_END_ON_LEN | \
119 MSGDMA_DESC_CTL_GO)
120
121/* mSGDMA extended descriptor stride definitions */
122#define MSGDMA_DESC_TX_STRIDE 0x00010001
123#define MSGDMA_DESC_RX_STRIDE 0x00010001
124
125/* mSGDMA dispatcher control and status register map */
126struct msgdma_csr {
127 u32 status; /* Read/Clear */
128 u32 control; /* Read/Write */
129 u32 rw_fill_level;
130 u32 resp_fill_level; /* bit 15:0 */
131 u32 rw_seq_num;
132 u32 pad[3]; /* reserved */
133};
134
135/* mSGDMA CSR status register bit definitions */
136#define MSGDMA_CSR_STAT_BUSY BIT(0)
137#define MSGDMA_CSR_STAT_RESETTING BIT(6)
138#define MSGDMA_CSR_STAT_MASK 0x3FF
139
140/* mSGDMA CSR control register bit definitions */
141#define MSGDMA_CSR_CTL_RESET BIT(1)
142
143/* mSGDMA response register map */
144struct msgdma_response {
145 u32 bytes_transferred;
146 u32 status;
147};
148
Thomas Chouc960b132010-04-20 12:49:52 +0800149/* TSE Stuff */
Thomas Chou4c8df1d2015-11-06 09:37:08 +0800150#define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
151#define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
152#define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
153#define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
154#define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
155#define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
Thomas Chouc960b132010-04-20 12:49:52 +0800156
Thomas Chou96fa1e42015-10-22 15:29:11 +0800157#define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
158#define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
Thomas Chouc960b132010-04-20 12:49:52 +0800159
160/* MAC register Space */
161
162struct alt_tse_mac {
Thomas Chou2cd0a522015-11-06 09:36:26 +0800163 u32 megacore_revision;
164 u32 scratch_pad;
165 u32 command_config;
166 u32 mac_addr_0;
167 u32 mac_addr_1;
168 u32 max_frame_length;
169 u32 pause_quanta;
170 u32 rx_sel_empty_threshold;
171 u32 rx_sel_full_threshold;
172 u32 tx_sel_empty_threshold;
173 u32 tx_sel_full_threshold;
174 u32 rx_almost_empty_threshold;
175 u32 rx_almost_full_threshold;
176 u32 tx_almost_empty_threshold;
177 u32 tx_almost_full_threshold;
178 u32 mdio_phy0_addr;
179 u32 mdio_phy1_addr;
Thomas Chouc960b132010-04-20 12:49:52 +0800180
Thomas Chou2cd0a522015-11-06 09:36:26 +0800181 u32 reserved1[0x29];
Thomas Chouc960b132010-04-20 12:49:52 +0800182
183 /*FIFO control register. */
Thomas Chou2cd0a522015-11-06 09:36:26 +0800184 u32 tx_cmd_stat;
185 u32 rx_cmd_stat;
Thomas Chouc960b132010-04-20 12:49:52 +0800186
Thomas Chou2cd0a522015-11-06 09:36:26 +0800187 u32 reserved2[0x44];
Thomas Chouc960b132010-04-20 12:49:52 +0800188
189 /*Registers 0 to 31 within PHY device 0/1 */
Thomas Chou2cd0a522015-11-06 09:36:26 +0800190 u32 mdio_phy0[0x20];
191 u32 mdio_phy1[0x20];
Thomas Chouc960b132010-04-20 12:49:52 +0800192
193 /*4 Supplemental MAC Addresses */
Thomas Chou2cd0a522015-11-06 09:36:26 +0800194 u32 supp_mac_addr_0_0;
195 u32 supp_mac_addr_0_1;
196 u32 supp_mac_addr_1_0;
197 u32 supp_mac_addr_1_1;
198 u32 supp_mac_addr_2_0;
199 u32 supp_mac_addr_2_1;
200 u32 supp_mac_addr_3_0;
201 u32 supp_mac_addr_3_1;
Thomas Chouc960b132010-04-20 12:49:52 +0800202
Thomas Chou2cd0a522015-11-06 09:36:26 +0800203 u32 reserved3[0x38];
Thomas Chouc960b132010-04-20 12:49:52 +0800204};
205
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800206struct tse_ops {
207 int (*send)(struct udevice *dev, void *packet, int length);
208 int (*recv)(struct udevice *dev, int flags, uchar **packetp);
209 int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
210 void (*stop)(struct udevice *dev);
211};
212
Thomas Chouc960b132010-04-20 12:49:52 +0800213struct altera_tse_priv {
Thomas Chou96fa1e42015-10-22 15:29:11 +0800214 struct alt_tse_mac *mac_dev;
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800215 void *sgdma_rx;
216 void *sgdma_tx;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800217 unsigned int rx_fifo_depth;
218 unsigned int tx_fifo_depth;
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800219 void *rx_desc;
220 void *tx_desc;
Thomas Choue3e87262015-11-09 14:36:29 +0800221 void *rx_resp;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800222 unsigned char *rx_buf;
Thomas Chouc960b132010-04-20 12:49:52 +0800223 unsigned int phyaddr;
Thomas Chou96fa1e42015-10-22 15:29:11 +0800224 unsigned int interface;
225 struct phy_device *phydev;
226 struct mii_dev *bus;
Thomas Chou38fa4ac2015-11-09 11:02:15 +0800227 const struct tse_ops *ops;
228 int dma_type;
Thomas Chouc960b132010-04-20 12:49:52 +0800229};
230
Thomas Chouc960b132010-04-20 12:49:52 +0800231#endif /* _ALTERA_TSE_H_ */