blob: 9db7bd80c2db1be7863329a2c137f8459e6e5eb2 [file] [log] [blame]
wdenk1df49e22002-09-17 21:37:55 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <malloc.h>
26#include <net.h>
27#include <asm/io.h>
28#include <pci.h>
29
30#undef DEBUG
31
32#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
33 defined(CONFIG_EEPRO100)
34
35 /* Ethernet chip registers.
36 */
37#define SCBStatus 0 /* Rx/Command Unit Status *Word* */
38#define SCBIntAckByte 1 /* Rx/Command Unit STAT/ACK byte */
39#define SCBCmd 2 /* Rx/Command Unit Command *Word* */
40#define SCBIntrCtlByte 3 /* Rx/Command Unit Intr.Control Byte */
41#define SCBPointer 4 /* General purpose pointer. */
42#define SCBPort 8 /* Misc. commands and operands. */
43#define SCBflash 12 /* Flash memory control. */
44#define SCBeeprom 14 /* EEPROM memory control. */
45#define SCBCtrlMDI 16 /* MDI interface control. */
46#define SCBEarlyRx 20 /* Early receive byte count. */
47#define SCBGenControl 28 /* 82559 General Control Register */
48#define SCBGenStatus 29 /* 82559 General Status register */
49
50 /* 82559 SCB status word defnitions
51 */
52#define SCB_STATUS_CX 0x8000 /* CU finished command (transmit) */
53#define SCB_STATUS_FR 0x4000 /* frame received */
54#define SCB_STATUS_CNA 0x2000 /* CU left active state */
55#define SCB_STATUS_RNR 0x1000 /* receiver left ready state */
56#define SCB_STATUS_MDI 0x0800 /* MDI read/write cycle done */
57#define SCB_STATUS_SWI 0x0400 /* software generated interrupt */
58#define SCB_STATUS_FCP 0x0100 /* flow control pause interrupt */
59
60#define SCB_INTACK_MASK 0xFD00 /* all the above */
61
62#define SCB_INTACK_TX (SCB_STATUS_CX | SCB_STATUS_CNA)
63#define SCB_INTACK_RX (SCB_STATUS_FR | SCB_STATUS_RNR)
64
65 /* System control block commands
66 */
67/* CU Commands */
68#define CU_NOP 0x0000
69#define CU_START 0x0010
70#define CU_RESUME 0x0020
71#define CU_STATSADDR 0x0040 /* Load Dump Statistics ctrs addr */
72#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */
73#define CU_ADDR_LOAD 0x0060 /* Base address to add to CU commands */
74#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */
75
76/* RUC Commands */
77#define RUC_NOP 0x0000
78#define RUC_START 0x0001
79#define RUC_RESUME 0x0002
80#define RUC_ABORT 0x0004
81#define RUC_ADDR_LOAD 0x0006 /* (seems not to clear on acceptance) */
82#define RUC_RESUMENR 0x0007
83
84#define CU_CMD_MASK 0x00f0
85#define RU_CMD_MASK 0x0007
86
87#define SCB_M 0x0100 /* 0 = enable interrupt, 1 = disable */
88#define SCB_SWI 0x0200 /* 1 - cause device to interrupt */
89
90#define CU_STATUS_MASK 0x00C0
91#define RU_STATUS_MASK 0x003C
92
93#define RU_STATUS_IDLE (0<<2)
94#define RU_STATUS_SUS (1<<2)
95#define RU_STATUS_NORES (2<<2)
96#define RU_STATUS_READY (4<<2)
97#define RU_STATUS_NO_RBDS_SUS ((1<<2)|(8<<2))
98#define RU_STATUS_NO_RBDS_NORES ((2<<2)|(8<<2))
99#define RU_STATUS_NO_RBDS_READY ((4<<2)|(8<<2))
100
101 /* 82559 Port interface commands.
102 */
103#define I82559_RESET 0x00000000 /* Software reset */
104#define I82559_SELFTEST 0x00000001 /* 82559 Selftest command */
105#define I82559_SELECTIVE_RESET 0x00000002
106#define I82559_DUMP 0x00000003
107#define I82559_DUMP_WAKEUP 0x00000007
108
109 /* 82559 Eeprom interface.
110 */
111#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */
112#define EE_CS 0x02 /* EEPROM chip select. */
113#define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
114#define EE_WRITE_0 0x01
115#define EE_WRITE_1 0x05
116#define EE_DATA_READ 0x08 /* EEPROM chip data out. */
117#define EE_ENB (0x4800 | EE_CS)
118#define EE_CMD_BITS 3
119#define EE_DATA_BITS 16
120
121 /* The EEPROM commands include the alway-set leading bit.
122 */
123#define EE_EWENB_CMD (4 << addr_len)
124#define EE_WRITE_CMD (5 << addr_len)
125#define EE_READ_CMD (6 << addr_len)
126#define EE_ERASE_CMD (7 << addr_len)
127
128 /* Receive frame descriptors.
129 */
130struct RxFD {
131 volatile u16 status;
132 volatile u16 control;
133 volatile u32 link; /* struct RxFD * */
134 volatile u32 rx_buf_addr; /* void * */
135 volatile u32 count;
136
137 volatile u8 data[PKTSIZE_ALIGN];
138};
139
140#define RFD_STATUS_C 0x8000 /* completion of received frame */
141#define RFD_STATUS_OK 0x2000 /* frame received with no errors */
142
143#define RFD_CONTROL_EL 0x8000 /* 1=last RFD in RFA */
144#define RFD_CONTROL_S 0x4000 /* 1=suspend RU after receiving frame */
145#define RFD_CONTROL_H 0x0010 /* 1=RFD is a header RFD */
146#define RFD_CONTROL_SF 0x0008 /* 0=simplified, 1=flexible mode */
147
148#define RFD_COUNT_MASK 0x3fff
149#define RFD_COUNT_F 0x4000
150#define RFD_COUNT_EOF 0x8000
151
152#define RFD_RX_CRC 0x0800 /* crc error */
153#define RFD_RX_ALIGNMENT 0x0400 /* alignment error */
154#define RFD_RX_RESOURCE 0x0200 /* out of space, no resources */
155#define RFD_RX_DMA_OVER 0x0100 /* DMA overrun */
156#define RFD_RX_SHORT 0x0080 /* short frame error */
157#define RFD_RX_LENGTH 0x0020
158#define RFD_RX_ERROR 0x0010 /* receive error */
159#define RFD_RX_NO_ADR_MATCH 0x0004 /* no address match */
160#define RFD_RX_IA_MATCH 0x0002 /* individual address does not match */
161#define RFD_RX_TCO 0x0001 /* TCO indication */
162
163 /* Transmit frame descriptors
164 */
165struct TxFD { /* Transmit frame descriptor set. */
166 volatile u16 status;
167 volatile u16 command;
168 volatile u32 link; /* void * */
169 volatile u32 tx_desc_addr; /* Always points to the tx_buf_addr element. */
170 volatile s32 count;
171
172 volatile u32 tx_buf_addr0; /* void *, frame to be transmitted. */
173 volatile s32 tx_buf_size0; /* Length of Tx frame. */
174 volatile u32 tx_buf_addr1; /* void *, frame to be transmitted. */
175 volatile s32 tx_buf_size1; /* Length of Tx frame. */
176};
177
178#define TxCB_CMD_TRANSMIT 0x0004 /* transmit command */
179#define TxCB_CMD_SF 0x0008 /* 0=simplified, 1=flexible mode */
180#define TxCB_CMD_NC 0x0010 /* 0=CRC insert by controller */
181#define TxCB_CMD_I 0x2000 /* generate interrupt on completion */
182#define TxCB_CMD_S 0x4000 /* suspend on completion */
183#define TxCB_CMD_EL 0x8000 /* last command block in CBL */
184
185#define TxCB_COUNT_MASK 0x3fff
186#define TxCB_COUNT_EOF 0x8000
187
188 /* The Speedo3 Rx and Tx frame/buffer descriptors.
189 */
190struct descriptor { /* A generic descriptor. */
191 volatile u16 status;
192 volatile u16 command;
193 volatile u32 link; /* struct descriptor * */
194
195 unsigned char params[0];
196};
197
198#define CFG_CMD_EL 0x8000
199#define CFG_CMD_SUSPEND 0x4000
200#define CFG_CMD_INT 0x2000
201#define CFG_CMD_IAS 0x0001 /* individual address setup */
202#define CFG_CMD_CONFIGURE 0x0002 /* configure */
203
204#define CFG_STATUS_C 0x8000
205#define CFG_STATUS_OK 0x2000
206
207 /* Misc.
208 */
209#define NUM_RX_DESC PKTBUFSRX
210#define NUM_TX_DESC 1 /* Number of TX descriptors */
211
212#define TOUT_LOOP 1000000
213
214#define ETH_ALEN 6
215
216static struct RxFD rx_ring[NUM_RX_DESC]; /* RX descriptor ring */
217static struct TxFD tx_ring[NUM_TX_DESC]; /* TX descriptor ring */
218static int rx_next; /* RX descriptor ring pointer */
219static int tx_next; /* TX descriptor ring pointer */
220static int tx_threshold;
221
222/*
223 * The parameters for a CmdConfigure operation.
224 * There are so many options that it would be difficult to document
225 * each bit. We mostly use the default or recommended settings.
226 */
227static const char i82557_config_cmd[] = {
228 22, 0x08, 0, 0, 0, 0, 0x32, 0x03, 1, /* 1=Use MII 0=Use AUI */
229 0, 0x2E, 0, 0x60, 0,
230 0xf2, 0x48, 0, 0x40, 0xf2, 0x80, /* 0x40=Force full-duplex */
231 0x3f, 0x05,
232};
233static const char i82558_config_cmd[] = {
234 22, 0x08, 0, 1, 0, 0, 0x22, 0x03, 1, /* 1=Use MII 0=Use AUI */
235 0, 0x2E, 0, 0x60, 0x08, 0x88,
236 0x68, 0, 0x40, 0xf2, 0x84, /* Disable FC */
237 0x31, 0x05,
238};
239
240static void init_rx_ring (struct eth_device *dev);
241static void purge_tx_ring (struct eth_device *dev);
242
243static void read_hw_addr (struct eth_device *dev, bd_t * bis);
244
245static int eepro100_init (struct eth_device *dev, bd_t * bis);
246static int eepro100_send (struct eth_device *dev, volatile void *packet,
247 int length);
248static int eepro100_recv (struct eth_device *dev);
249static void eepro100_halt (struct eth_device *dev);
250
wdenk3a473b22004-01-03 00:43:19 +0000251#if defined(CONFIG_E500) || defined(CONFIG_DB64360) || defined(CONFIG_DB64460)
wdenk42d1f032003-10-15 23:53:47 +0000252#define bus_to_phys(a) (a)
253#define phys_to_bus(a) (a)
254#else
wdenk1df49e22002-09-17 21:37:55 +0000255#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
256#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
wdenk42d1f032003-10-15 23:53:47 +0000257#endif
wdenk1df49e22002-09-17 21:37:55 +0000258
259static inline int INW (struct eth_device *dev, u_long addr)
260{
261 return le16_to_cpu (*(volatile u16 *) (addr + dev->iobase));
262}
263
264static inline void OUTW (struct eth_device *dev, int command, u_long addr)
265{
266 *(volatile u16 *) ((addr + dev->iobase)) = cpu_to_le16 (command);
267}
268
269static inline void OUTL (struct eth_device *dev, int command, u_long addr)
270{
271 *(volatile u32 *) ((addr + dev->iobase)) = cpu_to_le32 (command);
272}
273
Wolfgang Denka9127332005-09-26 00:39:59 +0200274#if defined (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
275static inline int INL (struct eth_device *dev, u_long addr)
276{
277 return le32_to_cpu (*(volatile u32 *) (addr + dev->iobase));
278}
279
280int miiphy_read (unsigned char addr,
281 unsigned char reg,
282 unsigned short *value)
283{
284 int cmd = (2 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
285
286 struct eth_device *dev = eth_get_dev ();
287
288 OUTL (dev, cmd, SCBCtrlMDI);
289
290 do {
291 cmd = INL (dev, SCBCtrlMDI);
292 } while (!(cmd & (1 << 28)));
293
294 *value = (unsigned short) (cmd & 0xffff);
295
296 return 0;
297}
298
299int miiphy_write (unsigned char addr,
300 unsigned char reg,
301 unsigned short value)
302{
303 int cmd = (1 << 26) | ((addr & 0x1f) << 21) | ((reg & 0x1f) << 16);
304
305 struct eth_device *dev = eth_get_dev ();
306
307 OUTL (dev, cmd | value, SCBCtrlMDI);
308
309 while (!(INL (dev, SCBCtrlMDI) & (1 << 28)));
310
311 return 0;
312}
313#endif /* (CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) */
314
wdenk1df49e22002-09-17 21:37:55 +0000315 /* Wait for the chip get the command.
316 */
317static int wait_for_eepro100 (struct eth_device *dev)
318{
319 int i;
320
321 for (i = 0; INW (dev, SCBCmd) & (CU_CMD_MASK | RU_CMD_MASK); i++) {
322 if (i >= TOUT_LOOP) {
323 return 0;
324 }
325 }
326
327 return 1;
328}
329
330static struct pci_device_id supported[] = {
331 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82557},
332 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559},
333 {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82559ER},
334 {}
335};
336
337int eepro100_initialize (bd_t * bis)
338{
339 pci_dev_t devno;
340 int card_number = 0;
341 struct eth_device *dev;
342 u32 iobase, status;
343 int idx = 0;
344
345 while (1) {
346 /* Find PCI device
347 */
348 if ((devno = pci_find_devices (supported, idx++)) < 0) {
349 break;
350 }
351
352 pci_read_config_dword (devno, PCI_BASE_ADDRESS_0, &iobase);
353 iobase &= ~0xf;
354
355#ifdef DEBUG
356 printf ("eepro100: Intel i82559 PCI EtherExpressPro @0x%x\n",
357 iobase);
358#endif
359
360 pci_write_config_dword (devno,
361 PCI_COMMAND,
362 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
363
364 /* Check if I/O accesses and Bus Mastering are enabled.
365 */
366 pci_read_config_dword (devno, PCI_COMMAND, &status);
367 if (!(status & PCI_COMMAND_MEMORY)) {
368 printf ("Error: Can not enable MEM access.\n");
369 continue;
370 }
371
372 if (!(status & PCI_COMMAND_MASTER)) {
373 printf ("Error: Can not enable Bus Mastering.\n");
374 continue;
375 }
376
377 dev = (struct eth_device *) malloc (sizeof *dev);
378
379 sprintf (dev->name, "i82559#%d", card_number);
wdenk7a8e9bed2003-05-31 18:35:21 +0000380 dev->priv = (void *) devno; /* this have to come before bus_to_phys() */
wdenk1df49e22002-09-17 21:37:55 +0000381 dev->iobase = bus_to_phys (iobase);
wdenk1df49e22002-09-17 21:37:55 +0000382 dev->init = eepro100_init;
383 dev->halt = eepro100_halt;
384 dev->send = eepro100_send;
385 dev->recv = eepro100_recv;
386
387 eth_register (dev);
388
389 card_number++;
390
391 /* Set the latency timer for value.
392 */
393 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
394
395 udelay (10 * 1000);
396
397 read_hw_addr (dev, bis);
398 }
399
400 return card_number;
401}
402
403
404static int eepro100_init (struct eth_device *dev, bd_t * bis)
405{
406 int i, status = 0;
407 int tx_cur;
408 struct descriptor *ias_cmd, *cfg_cmd;
409
410 /* Reset the ethernet controller
411 */
412 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
413 udelay (20);
414
415 OUTL (dev, I82559_RESET, SCBPort);
416 udelay (20);
417
418 if (!wait_for_eepro100 (dev)) {
419 printf ("Error: Can not reset ethernet controller.\n");
420 goto Done;
421 }
422 OUTL (dev, 0, SCBPointer);
423 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
424
425 if (!wait_for_eepro100 (dev)) {
426 printf ("Error: Can not reset ethernet controller.\n");
427 goto Done;
428 }
429 OUTL (dev, 0, SCBPointer);
430 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
431
432 /* Initialize Rx and Tx rings.
433 */
434 init_rx_ring (dev);
435 purge_tx_ring (dev);
436
437 /* Tell the adapter where the RX ring is located.
438 */
439 if (!wait_for_eepro100 (dev)) {
440 printf ("Error: Can not reset ethernet controller.\n");
441 goto Done;
442 }
443
444 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
445 OUTW (dev, SCB_M | RUC_START, SCBCmd);
446
447 /* Send the Configure frame */
448 tx_cur = tx_next;
449 tx_next = ((tx_next + 1) % NUM_TX_DESC);
450
451 cfg_cmd = (struct descriptor *) &tx_ring[tx_cur];
452 cfg_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_CONFIGURE));
453 cfg_cmd->status = 0;
454 cfg_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
455
456 memcpy (cfg_cmd->params, i82558_config_cmd,
457 sizeof (i82558_config_cmd));
458
459 if (!wait_for_eepro100 (dev)) {
460 printf ("Error---CFG_CMD_CONFIGURE: Can not reset ethernet controller.\n");
461 goto Done;
462 }
463
464 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
465 OUTW (dev, SCB_M | CU_START, SCBCmd);
466
467 for (i = 0;
468 !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
469 i++) {
470 if (i >= TOUT_LOOP) {
471 printf ("%s: Tx error buffer not ready\n", dev->name);
472 goto Done;
473 }
474 }
475
476 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
477 printf ("TX error status = 0x%08X\n",
478 le16_to_cpu (tx_ring[tx_cur].status));
479 goto Done;
480 }
481
482 /* Send the Individual Address Setup frame
483 */
484 tx_cur = tx_next;
485 tx_next = ((tx_next + 1) % NUM_TX_DESC);
486
487 ias_cmd = (struct descriptor *) &tx_ring[tx_cur];
488 ias_cmd->command = cpu_to_le16 ((CFG_CMD_SUSPEND | CFG_CMD_IAS));
489 ias_cmd->status = 0;
490 ias_cmd->link = cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
491
492 memcpy (ias_cmd->params, dev->enetaddr, 6);
493
494 /* Tell the adapter where the TX ring is located.
495 */
496 if (!wait_for_eepro100 (dev)) {
497 printf ("Error: Can not reset ethernet controller.\n");
498 goto Done;
499 }
500
501 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
502 OUTW (dev, SCB_M | CU_START, SCBCmd);
503
504 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
505 i++) {
506 if (i >= TOUT_LOOP) {
507 printf ("%s: Tx error buffer not ready\n",
508 dev->name);
509 goto Done;
510 }
511 }
512
513 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
514 printf ("TX error status = 0x%08X\n",
515 le16_to_cpu (tx_ring[tx_cur].status));
516 goto Done;
517 }
518
519 status = 1;
520
521 Done:
522 return status;
523}
524
525static int eepro100_send (struct eth_device *dev, volatile void *packet, int length)
526{
527 int i, status = -1;
528 int tx_cur;
529
530 if (length <= 0) {
531 printf ("%s: bad packet size: %d\n", dev->name, length);
532 goto Done;
533 }
534
535 tx_cur = tx_next;
536 tx_next = (tx_next + 1) % NUM_TX_DESC;
537
538 tx_ring[tx_cur].command = cpu_to_le16 ( TxCB_CMD_TRANSMIT |
539 TxCB_CMD_SF |
540 TxCB_CMD_S |
541 TxCB_CMD_EL );
542 tx_ring[tx_cur].status = 0;
543 tx_ring[tx_cur].count = cpu_to_le32 (tx_threshold);
544 tx_ring[tx_cur].link =
545 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_next]));
546 tx_ring[tx_cur].tx_desc_addr =
547 cpu_to_le32 (phys_to_bus ((u32) & tx_ring[tx_cur].tx_buf_addr0));
548 tx_ring[tx_cur].tx_buf_addr0 =
549 cpu_to_le32 (phys_to_bus ((u_long) packet));
550 tx_ring[tx_cur].tx_buf_size0 = cpu_to_le32 (length);
551
552 if (!wait_for_eepro100 (dev)) {
553 printf ("%s: Tx error ethernet controller not ready.\n",
554 dev->name);
555 goto Done;
556 }
557
558 /* Send the packet.
559 */
560 OUTL (dev, phys_to_bus ((u32) & tx_ring[tx_cur]), SCBPointer);
561 OUTW (dev, SCB_M | CU_START, SCBCmd);
562
563 for (i = 0; !(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_C);
564 i++) {
565 if (i >= TOUT_LOOP) {
566 printf ("%s: Tx error buffer not ready\n", dev->name);
567 goto Done;
568 }
569 }
570
571 if (!(le16_to_cpu (tx_ring[tx_cur].status) & CFG_STATUS_OK)) {
572 printf ("TX error status = 0x%08X\n",
573 le16_to_cpu (tx_ring[tx_cur].status));
574 goto Done;
575 }
576
577 status = length;
578
579 Done:
580 return status;
581}
582
583static int eepro100_recv (struct eth_device *dev)
584{
585 u16 status, stat;
586 int rx_prev, length = 0;
587
588 stat = INW (dev, SCBStatus);
589 OUTW (dev, stat & SCB_STATUS_RNR, SCBStatus);
590
591 for (;;) {
592 status = le16_to_cpu (rx_ring[rx_next].status);
593
594 if (!(status & RFD_STATUS_C)) {
595 break;
596 }
597
598 /* Valid frame status.
599 */
600 if ((status & RFD_STATUS_OK)) {
601 /* A valid frame received.
602 */
603 length = le32_to_cpu (rx_ring[rx_next].count) & 0x3fff;
604
605 /* Pass the packet up to the protocol
606 * layers.
607 */
608 NetReceive (rx_ring[rx_next].data, length);
609 } else {
610 /* There was an error.
611 */
612 printf ("RX error status = 0x%08X\n", status);
613 }
614
615 rx_ring[rx_next].control = cpu_to_le16 (RFD_CONTROL_S);
616 rx_ring[rx_next].status = 0;
617 rx_ring[rx_next].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
618
619 rx_prev = (rx_next + NUM_RX_DESC - 1) % NUM_RX_DESC;
620 rx_ring[rx_prev].control = 0;
621
622 /* Update entry information.
623 */
624 rx_next = (rx_next + 1) % NUM_RX_DESC;
625 }
626
627 if (stat & SCB_STATUS_RNR) {
628
629 printf ("%s: Receiver is not ready, restart it !\n", dev->name);
630
631 /* Reinitialize Rx ring.
632 */
633 init_rx_ring (dev);
634
635 if (!wait_for_eepro100 (dev)) {
636 printf ("Error: Can not restart ethernet controller.\n");
637 goto Done;
638 }
639
640 OUTL (dev, phys_to_bus ((u32) & rx_ring[rx_next]), SCBPointer);
641 OUTW (dev, SCB_M | RUC_START, SCBCmd);
642 }
643
644 Done:
645 return length;
646}
647
648static void eepro100_halt (struct eth_device *dev)
649{
650 /* Reset the ethernet controller
651 */
652 OUTL (dev, I82559_SELECTIVE_RESET, SCBPort);
653 udelay (20);
654
655 OUTL (dev, I82559_RESET, SCBPort);
656 udelay (20);
657
658 if (!wait_for_eepro100 (dev)) {
659 printf ("Error: Can not reset ethernet controller.\n");
660 goto Done;
661 }
662 OUTL (dev, 0, SCBPointer);
663 OUTW (dev, SCB_M | RUC_ADDR_LOAD, SCBCmd);
664
665 if (!wait_for_eepro100 (dev)) {
666 printf ("Error: Can not reset ethernet controller.\n");
667 goto Done;
668 }
669 OUTL (dev, 0, SCBPointer);
670 OUTW (dev, SCB_M | CU_ADDR_LOAD, SCBCmd);
671
672 Done:
673 return;
674}
675
676 /* SROM Read.
677 */
678static int read_eeprom (struct eth_device *dev, int location, int addr_len)
679{
680 unsigned short retval = 0;
681 int read_cmd = location | EE_READ_CMD;
682 int i;
683
684 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
685 OUTW (dev, EE_ENB, SCBeeprom);
686
687 /* Shift the read command bits out. */
688 for (i = 12; i >= 0; i--) {
689 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
690
691 OUTW (dev, EE_ENB | dataval, SCBeeprom);
692 udelay (1);
693 OUTW (dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
694 udelay (1);
695 }
696 OUTW (dev, EE_ENB, SCBeeprom);
697
698 for (i = 15; i >= 0; i--) {
699 OUTW (dev, EE_ENB | EE_SHIFT_CLK, SCBeeprom);
700 udelay (1);
701 retval = (retval << 1) |
702 ((INW (dev, SCBeeprom) & EE_DATA_READ) ? 1 : 0);
703 OUTW (dev, EE_ENB, SCBeeprom);
704 udelay (1);
705 }
706
707 /* Terminate the EEPROM access. */
708 OUTW (dev, EE_ENB & ~EE_CS, SCBeeprom);
709 return retval;
710}
711
712#ifdef CONFIG_EEPRO100_SROM_WRITE
713int eepro100_write_eeprom (struct eth_device* dev, int location, int addr_len, unsigned short data)
714{
715 unsigned short dataval;
716 int enable_cmd = 0x3f | EE_EWENB_CMD;
717 int write_cmd = location | EE_WRITE_CMD;
718 int i;
719 unsigned long datalong, tmplong;
720
721 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
722 udelay(1);
723 OUTW(dev, EE_ENB, SCBeeprom);
724
725 /* Shift the enable command bits out. */
726 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
727 {
wdenk8bde7f72003-06-27 21:31:46 +0000728 dataval = (enable_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
729 OUTW(dev, EE_ENB | dataval, SCBeeprom);
730 udelay(1);
731 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
732 udelay(1);
wdenk1df49e22002-09-17 21:37:55 +0000733 }
734
735 OUTW(dev, EE_ENB, SCBeeprom);
736 udelay(1);
737 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
738 udelay(1);
739 OUTW(dev, EE_ENB, SCBeeprom);
740
741
742 /* Shift the write command bits out. */
743 for (i = (addr_len+EE_CMD_BITS-1); i >= 0; i--)
744 {
wdenk8bde7f72003-06-27 21:31:46 +0000745 dataval = (write_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
746 OUTW(dev, EE_ENB | dataval, SCBeeprom);
747 udelay(1);
748 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
749 udelay(1);
wdenk1df49e22002-09-17 21:37:55 +0000750 }
751
752 /* Write the data */
753 datalong= (unsigned long) ((((data) & 0x00ff) << 8) | ( (data) >> 8));
754
755 for (i = 0; i< EE_DATA_BITS; i++)
756 {
757 /* Extract and move data bit to bit DI */
758 dataval = ((datalong & 0x8000)>>13) ? EE_DATA_WRITE : 0;
759
760 OUTW(dev, EE_ENB | dataval, SCBeeprom);
761 udelay(1);
762 OUTW(dev, EE_ENB | dataval | EE_SHIFT_CLK, SCBeeprom);
763 udelay(1);
764 OUTW(dev, EE_ENB | dataval, SCBeeprom);
765 udelay(1);
766
767 datalong = datalong << 1; /* Adjust significant data bit*/
768 }
769
770 /* Finish up command (toggle CS) */
771 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
772 udelay(1); /* delay for more than 250 ns */
773 OUTW(dev, EE_ENB, SCBeeprom);
774
775 /* Wait for programming ready (D0 = 1) */
776 tmplong = 10;
777 do
778 {
wdenk8bde7f72003-06-27 21:31:46 +0000779 dataval = INW(dev, SCBeeprom);
780 if (dataval & EE_DATA_READ)
781 break;
782 udelay(10000);
wdenk1df49e22002-09-17 21:37:55 +0000783 }
784 while (-- tmplong);
785
786 if (tmplong == 0)
787 {
wdenk8bde7f72003-06-27 21:31:46 +0000788 printf ("Write i82559 eeprom timed out (100 ms waiting for data ready.\n");
789 return -1;
wdenk1df49e22002-09-17 21:37:55 +0000790 }
791
792 /* Terminate the EEPROM access. */
793 OUTW(dev, EE_ENB & ~EE_CS, SCBeeprom);
794
795 return 0;
796}
797#endif
798
799static void init_rx_ring (struct eth_device *dev)
800{
801 int i;
802
803 for (i = 0; i < NUM_RX_DESC; i++) {
804 rx_ring[i].status = 0;
805 rx_ring[i].control =
806 (i == NUM_RX_DESC - 1) ? cpu_to_le16 (RFD_CONTROL_S) : 0;
807 rx_ring[i].link =
808 cpu_to_le32 (phys_to_bus
809 ((u32) & rx_ring[(i + 1) % NUM_RX_DESC]));
810 rx_ring[i].rx_buf_addr = 0xffffffff;
811 rx_ring[i].count = cpu_to_le32 (PKTSIZE_ALIGN << 16);
812 }
813
814 rx_next = 0;
815}
816
817static void purge_tx_ring (struct eth_device *dev)
818{
819 int i;
820
821 tx_next = 0;
822 tx_threshold = 0x01208000;
823
824 for (i = 0; i < NUM_TX_DESC; i++) {
825 tx_ring[i].status = 0;
826 tx_ring[i].command = 0;
827 tx_ring[i].link = 0;
828 tx_ring[i].tx_desc_addr = 0;
829 tx_ring[i].count = 0;
830
831 tx_ring[i].tx_buf_addr0 = 0;
832 tx_ring[i].tx_buf_size0 = 0;
833 tx_ring[i].tx_buf_addr1 = 0;
834 tx_ring[i].tx_buf_size1 = 0;
835 }
836}
837
838static void read_hw_addr (struct eth_device *dev, bd_t * bis)
839{
840 u16 eeprom[0x40];
841 u16 sum = 0;
842 int i, j;
843 int addr_len = read_eeprom (dev, 0, 6) == 0xffff ? 8 : 6;
844
845 for (j = 0, i = 0; i < 0x40; i++) {
846 u16 value = read_eeprom (dev, i, addr_len);
847
848 eeprom[i] = value;
849 sum += value;
850 if (i < 3) {
851 dev->enetaddr[j++] = value;
852 dev->enetaddr[j++] = value >> 8;
853 }
854 }
855
856 if (sum != 0xBABA) {
857 memset (dev->enetaddr, 0, ETH_ALEN);
858#ifdef DEBUG
859 printf ("%s: Invalid EEPROM checksum %#4.4x, "
860 "check settings before activating this device!\n",
861 dev->name, sum);
862#endif
863 }
864}
865
866#endif