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Andy Fleming9082eea2011-04-07 21:56:05 -05001/*
2 * Marvell PHY drivers
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming9082eea2011-04-07 21:56:05 -05005 *
6 * Copyright 2010-2011 Freescale Semiconductor, Inc.
7 * author Andy Fleming
Andy Fleming9082eea2011-04-07 21:56:05 -05008 */
9#include <config.h>
10#include <common.h>
11#include <phy.h>
12
13#define PHY_AUTONEGOTIATE_TIMEOUT 5000
14
15/* 88E1011 PHY Status Register */
16#define MIIM_88E1xxx_PHY_STATUS 0x11
17#define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000
18#define MIIM_88E1xxx_PHYSTAT_GBIT 0x8000
19#define MIIM_88E1xxx_PHYSTAT_100 0x4000
20#define MIIM_88E1xxx_PHYSTAT_DUPLEX 0x2000
21#define MIIM_88E1xxx_PHYSTAT_SPDDONE 0x0800
22#define MIIM_88E1xxx_PHYSTAT_LINK 0x0400
23
24#define MIIM_88E1xxx_PHY_SCR 0x10
25#define MIIM_88E1xxx_PHY_MDI_X_AUTO 0x0060
26
27/* 88E1111 PHY LED Control Register */
28#define MIIM_88E1111_PHY_LED_CONTROL 24
29#define MIIM_88E1111_PHY_LED_DIRECT 0x4100
30#define MIIM_88E1111_PHY_LED_COMBINE 0x411C
31
Zang Roy-R61911fa12a082011-10-27 18:52:09 +000032/* 88E1111 Extended PHY Specific Control Register */
33#define MIIM_88E1111_PHY_EXT_CR 0x14
34#define MIIM_88E1111_RX_DELAY 0x80
35#define MIIM_88E1111_TX_DELAY 0x2
36
37/* 88E1111 Extended PHY Specific Status Register */
38#define MIIM_88E1111_PHY_EXT_SR 0x1b
39#define MIIM_88E1111_HWCFG_MODE_MASK 0xf
40#define MIIM_88E1111_HWCFG_MODE_COPPER_RGMII 0xb
41#define MIIM_88E1111_HWCFG_MODE_FIBER_RGMII 0x3
42#define MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK 0x4
43#define MIIM_88E1111_HWCFG_MODE_COPPER_RTBI 0x9
44#define MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO 0x8000
45#define MIIM_88E1111_HWCFG_FIBER_COPPER_RES 0x2000
46
47#define MIIM_88E1111_COPPER 0
48#define MIIM_88E1111_FIBER 1
49
Andy Fleming9082eea2011-04-07 21:56:05 -050050/* 88E1118 PHY defines */
51#define MIIM_88E1118_PHY_PAGE 22
52#define MIIM_88E1118_PHY_LED_PAGE 3
53
54/* 88E1121 PHY LED Control Register */
55#define MIIM_88E1121_PHY_LED_CTRL 16
56#define MIIM_88E1121_PHY_LED_PAGE 3
57#define MIIM_88E1121_PHY_LED_DEF 0x0030
58
59/* 88E1121 PHY IRQ Enable/Status Register */
60#define MIIM_88E1121_PHY_IRQ_EN 18
61#define MIIM_88E1121_PHY_IRQ_STATUS 19
62
63#define MIIM_88E1121_PHY_PAGE 22
64
65/* 88E1145 Extended PHY Specific Control Register */
66#define MIIM_88E1145_PHY_EXT_CR 20
67#define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
68#define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
69
70#define MIIM_88E1145_PHY_LED_CONTROL 24
71#define MIIM_88E1145_PHY_LED_DIRECT 0x4100
72
73#define MIIM_88E1145_PHY_PAGE 29
74#define MIIM_88E1145_PHY_CAL_OV 30
75
76#define MIIM_88E1149_PHY_PAGE 29
77
Sebastian Hesselbarthaeceec02012-12-04 09:31:59 +010078/* 88E1310 PHY defines */
79#define MIIM_88E1310_PHY_LED_CTRL 16
80#define MIIM_88E1310_PHY_IRQ_EN 18
81#define MIIM_88E1310_PHY_RGMII_CTRL 21
82#define MIIM_88E1310_PHY_PAGE 22
83
Andy Fleming9082eea2011-04-07 21:56:05 -050084/* Marvell 88E1011S */
85static int m88e1011s_config(struct phy_device *phydev)
86{
87 /* Reset and configure the PHY */
88 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
89
90 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
91 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
92 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
93 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0);
94 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
95
96 phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_RESET);
97
98 genphy_config_aneg(phydev);
99
100 return 0;
101}
102
103/* Parse the 88E1011's status register for speed and duplex
104 * information
105 */
106static uint m88e1xxx_parse_status(struct phy_device *phydev)
107{
108 unsigned int speed;
109 unsigned int mii_reg;
110
111 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS);
112
113 if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) &&
114 !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
115 int i = 0;
116
117 puts("Waiting for PHY realtime link");
118 while (!(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) {
119 /* Timeout reached ? */
120 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
121 puts(" TIMEOUT !\n");
122 phydev->link = 0;
123 break;
124 }
125
126 if ((i++ % 1000) == 0)
127 putc('.');
128 udelay(1000);
129 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
130 MIIM_88E1xxx_PHY_STATUS);
131 }
132 puts(" done\n");
133 udelay(500000); /* another 500 ms (results in faster booting) */
134 } else {
135 if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK)
136 phydev->link = 1;
137 else
138 phydev->link = 0;
139 }
140
141 if (mii_reg & MIIM_88E1xxx_PHYSTAT_DUPLEX)
142 phydev->duplex = DUPLEX_FULL;
143 else
144 phydev->duplex = DUPLEX_HALF;
145
146 speed = mii_reg & MIIM_88E1xxx_PHYSTAT_SPEED;
147
148 switch (speed) {
149 case MIIM_88E1xxx_PHYSTAT_GBIT:
150 phydev->speed = SPEED_1000;
151 break;
152 case MIIM_88E1xxx_PHYSTAT_100:
153 phydev->speed = SPEED_100;
154 break;
155 default:
156 phydev->speed = SPEED_10;
157 break;
158 }
159
160 return 0;
161}
162
163static int m88e1011s_startup(struct phy_device *phydev)
164{
165 genphy_update_link(phydev);
166 m88e1xxx_parse_status(phydev);
167
168 return 0;
169}
170
171/* Marvell 88E1111S */
172static int m88e1111s_config(struct phy_device *phydev)
173{
174 int reg;
175
176 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
177 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
178 (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) ||
179 (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) {
Zang Roy-R61911fa12a082011-10-27 18:52:09 +0000180 reg = phy_read(phydev,
181 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
182 if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
183 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) {
184 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
185 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
186 reg &= ~MIIM_88E1111_TX_DELAY;
187 reg |= MIIM_88E1111_RX_DELAY;
188 } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
189 reg &= ~MIIM_88E1111_RX_DELAY;
190 reg |= MIIM_88E1111_TX_DELAY;
191 }
192
193 phy_write(phydev,
194 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
195
196 reg = phy_read(phydev,
197 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
198
199 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
200
201 if (reg & MIIM_88E1111_HWCFG_FIBER_COPPER_RES)
202 reg |= MIIM_88E1111_HWCFG_MODE_FIBER_RGMII;
203 else
204 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII;
205
206 phy_write(phydev,
207 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg);
Andy Fleming9082eea2011-04-07 21:56:05 -0500208 }
209
Zang Roy-R61911fa12a082011-10-27 18:52:09 +0000210 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
211 reg = phy_read(phydev,
212 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR);
213
214 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK);
215 reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK;
216 reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
217
218 phy_write(phydev, MDIO_DEVAD_NONE,
219 MIIM_88E1111_PHY_EXT_SR, reg);
220 }
221
222 if (phydev->interface == PHY_INTERFACE_MODE_RTBI) {
223 reg = phy_read(phydev,
224 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR);
225 reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY);
226 phy_write(phydev,
227 MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg);
228
229 reg = phy_read(phydev, MDIO_DEVAD_NONE,
230 MIIM_88E1111_PHY_EXT_SR);
231 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
232 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
233 reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
234 phy_write(phydev, MDIO_DEVAD_NONE,
235 MIIM_88E1111_PHY_EXT_SR, reg);
236
237 /* soft reset */
Stefan Roese3089c472016-02-10 07:06:05 +0100238 phy_reset(phydev);
Zang Roy-R61911fa12a082011-10-27 18:52:09 +0000239
240 reg = phy_read(phydev, MDIO_DEVAD_NONE,
241 MIIM_88E1111_PHY_EXT_SR);
242 reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK |
243 MIIM_88E1111_HWCFG_FIBER_COPPER_RES);
244 reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI |
245 MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO;
246 phy_write(phydev, MDIO_DEVAD_NONE,
247 MIIM_88E1111_PHY_EXT_SR, reg);
248 }
249
250 /* soft reset */
Stefan Roese3089c472016-02-10 07:06:05 +0100251 phy_reset(phydev);
Andy Fleming9082eea2011-04-07 21:56:05 -0500252
253 genphy_config_aneg(phydev);
Stefan Roesea8c3eca2016-02-10 07:06:06 +0100254 genphy_restart_aneg(phydev);
Andy Fleming9082eea2011-04-07 21:56:05 -0500255
256 return 0;
257}
258
Hao Zhang35fa0dd2014-10-30 18:59:43 +0200259/**
260 * m88e1518_phy_writebits - write bits to a register
261 */
262void m88e1518_phy_writebits(struct phy_device *phydev,
263 u8 reg_num, u16 offset, u16 len, u16 data)
264{
265 u16 reg, mask;
266
267 if ((len + offset) >= 16)
268 mask = 0 - (1 << offset);
269 else
270 mask = (1 << (len + offset)) - (1 << offset);
271
272 reg = phy_read(phydev, MDIO_DEVAD_NONE, reg_num);
273
274 reg &= ~mask;
275 reg |= data << offset;
276
277 phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg);
278}
279
280static int m88e1518_config(struct phy_device *phydev)
281{
282 /*
283 * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512
284 * /88E1514 Rev A0, Errata Section 3.1
285 */
Clemens Gruber90a94ef2015-06-06 14:44:57 +0200286
287 /* EEE initialization */
288 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff);
289 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B);
290 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144);
291 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28);
292 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2146);
293 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xB233);
294 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D);
295 phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C);
296 phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159);
297 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000);
298
299 /* SGMII-to-Copper mode initialization */
Hao Zhang35fa0dd2014-10-30 18:59:43 +0200300 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
Clemens Gruber90a94ef2015-06-06 14:44:57 +0200301 /* Select page 18 */
302 phy_write(phydev, MDIO_DEVAD_NONE, 22, 18);
303
304 /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */
Hao Zhang35fa0dd2014-10-30 18:59:43 +0200305 m88e1518_phy_writebits(phydev, 20, 0, 3, 1);
306
Clemens Gruber90a94ef2015-06-06 14:44:57 +0200307 /* PHY reset is necessary after changing MODE[2:0] */
Hao Zhang35fa0dd2014-10-30 18:59:43 +0200308 m88e1518_phy_writebits(phydev, 20, 15, 1, 1);
Clemens Gruber90a94ef2015-06-06 14:44:57 +0200309
310 /* Reset page selection */
311 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
312
Hao Zhang35fa0dd2014-10-30 18:59:43 +0200313 udelay(100);
314 }
315
316 return m88e1111s_config(phydev);
317}
318
Clemens Gruber8396d0a2015-06-06 14:44:58 +0200319/* Marvell 88E1510 */
320static int m88e1510_config(struct phy_device *phydev)
321{
322 /* Select page 3 */
323 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
324
325 /* Enable INTn output on LED[2] */
326 m88e1518_phy_writebits(phydev, 18, 7, 1, 1);
327
328 /* Configure LEDs */
329 m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */
330 m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */
331
332 /* Reset page selection */
333 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
334
335 return m88e1518_config(phydev);
336}
337
Andy Fleming9082eea2011-04-07 21:56:05 -0500338/* Marvell 88E1118 */
339static int m88e1118_config(struct phy_device *phydev)
340{
341 /* Change Page Number */
342 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0002);
343 /* Delay RGMII TX and RX */
344 phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x1070);
345 /* Change Page Number */
346 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0003);
347 /* Adjust LED control */
348 phy_write(phydev, MDIO_DEVAD_NONE, 0x10, 0x021e);
349 /* Change Page Number */
350 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
351
352 genphy_config_aneg(phydev);
353
354 phy_reset(phydev);
355
356 return 0;
357}
358
359static int m88e1118_startup(struct phy_device *phydev)
360{
361 /* Change Page Number */
362 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000);
363
364 genphy_update_link(phydev);
365 m88e1xxx_parse_status(phydev);
366
367 return 0;
368}
369
370/* Marvell 88E1121R */
371static int m88e1121_config(struct phy_device *phydev)
372{
373 int pg;
374
375 /* Configure the PHY */
376 genphy_config_aneg(phydev);
377
378 /* Switch the page to access the led register */
379 pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE);
380 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE,
381 MIIM_88E1121_PHY_LED_PAGE);
382 /* Configure leds */
383 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL,
384 MIIM_88E1121_PHY_LED_DEF);
385 /* Restore the page pointer */
386 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg);
387
388 /* Disable IRQs and de-assert interrupt */
389 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_EN, 0);
390 phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_IRQ_STATUS);
391
392 return 0;
393}
394
395/* Marvell 88E1145 */
396static int m88e1145_config(struct phy_device *phydev)
397{
398 int reg;
399
400 /* Errata E0, E1 */
401 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x001b);
402 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0x418f);
403 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_PAGE, 0x0016);
404 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da);
405
406 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR,
407 MIIM_88E1xxx_PHY_MDI_X_AUTO);
408
409 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR);
410 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
411 reg |= MIIM_M88E1145_RGMII_RX_DELAY |
412 MIIM_M88E1145_RGMII_TX_DELAY;
413 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR, reg);
414
415 genphy_config_aneg(phydev);
416
417 phy_reset(phydev);
418
419 return 0;
420}
421
422static int m88e1145_startup(struct phy_device *phydev)
423{
424 genphy_update_link(phydev);
425 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL,
426 MIIM_88E1145_PHY_LED_DIRECT);
427 m88e1xxx_parse_status(phydev);
428
429 return 0;
430}
431
432/* Marvell 88E1149S */
433static int m88e1149_config(struct phy_device *phydev)
434{
435 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x1f);
436 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x200c);
437 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1149_PHY_PAGE, 0x5);
438 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x0);
439 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
440
441 genphy_config_aneg(phydev);
442
443 phy_reset(phydev);
444
445 return 0;
446}
447
Sebastian Hesselbarthaeceec02012-12-04 09:31:59 +0100448/* Marvell 88E1310 */
449static int m88e1310_config(struct phy_device *phydev)
450{
451 u16 reg;
452
453 /* LED link and activity */
454 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
455 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
456 reg = (reg & ~0xf) | 0x1;
457 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
458
459 /* Set LED2/INT to INT mode, low active */
460 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
461 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
462 reg = (reg & 0x77ff) | 0x0880;
463 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
464
465 /* Set RGMII delay */
466 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
467 reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
468 reg |= 0x0030;
469 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
470
471 /* Ensure to return to page 0 */
472 phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000);
473
474 genphy_config_aneg(phydev);
475 phy_reset(phydev);
476
477 return 0;
478}
Andy Fleming9082eea2011-04-07 21:56:05 -0500479
480static struct phy_driver M88E1011S_driver = {
481 .name = "Marvell 88E1011S",
482 .uid = 0x1410c60,
483 .mask = 0xffffff0,
484 .features = PHY_GBIT_FEATURES,
485 .config = &m88e1011s_config,
486 .startup = &m88e1011s_startup,
487 .shutdown = &genphy_shutdown,
488};
489
490static struct phy_driver M88E1111S_driver = {
491 .name = "Marvell 88E1111S",
492 .uid = 0x1410cc0,
493 .mask = 0xffffff0,
494 .features = PHY_GBIT_FEATURES,
495 .config = &m88e1111s_config,
496 .startup = &m88e1011s_startup,
497 .shutdown = &genphy_shutdown,
498};
499
500static struct phy_driver M88E1118_driver = {
501 .name = "Marvell 88E1118",
502 .uid = 0x1410e10,
503 .mask = 0xffffff0,
504 .features = PHY_GBIT_FEATURES,
505 .config = &m88e1118_config,
506 .startup = &m88e1118_startup,
507 .shutdown = &genphy_shutdown,
508};
509
Michal Simekb4b81e82012-08-07 02:23:07 +0000510static struct phy_driver M88E1118R_driver = {
511 .name = "Marvell 88E1118R",
512 .uid = 0x1410e40,
513 .mask = 0xffffff0,
514 .features = PHY_GBIT_FEATURES,
515 .config = &m88e1118_config,
516 .startup = &m88e1118_startup,
517 .shutdown = &genphy_shutdown,
518};
519
Andy Fleming9082eea2011-04-07 21:56:05 -0500520static struct phy_driver M88E1121R_driver = {
521 .name = "Marvell 88E1121R",
522 .uid = 0x1410cb0,
523 .mask = 0xffffff0,
524 .features = PHY_GBIT_FEATURES,
525 .config = &m88e1121_config,
526 .startup = &genphy_startup,
527 .shutdown = &genphy_shutdown,
528};
529
530static struct phy_driver M88E1145_driver = {
531 .name = "Marvell 88E1145",
532 .uid = 0x1410cd0,
533 .mask = 0xffffff0,
534 .features = PHY_GBIT_FEATURES,
535 .config = &m88e1145_config,
536 .startup = &m88e1145_startup,
537 .shutdown = &genphy_shutdown,
538};
539
540static struct phy_driver M88E1149S_driver = {
541 .name = "Marvell 88E1149S",
542 .uid = 0x1410ca0,
543 .mask = 0xffffff0,
544 .features = PHY_GBIT_FEATURES,
545 .config = &m88e1149_config,
546 .startup = &m88e1011s_startup,
547 .shutdown = &genphy_shutdown,
548};
549
Clemens Gruber8396d0a2015-06-06 14:44:58 +0200550static struct phy_driver M88E1510_driver = {
551 .name = "Marvell 88E1510",
552 .uid = 0x1410dd0,
553 .mask = 0xffffff0,
554 .features = PHY_GBIT_FEATURES,
555 .config = &m88e1510_config,
556 .startup = &m88e1011s_startup,
557 .shutdown = &genphy_shutdown,
558};
559
Michal Simek14151072012-10-15 14:03:00 +0200560static struct phy_driver M88E1518_driver = {
561 .name = "Marvell 88E1518",
562 .uid = 0x1410dd1,
563 .mask = 0xffffff0,
564 .features = PHY_GBIT_FEATURES,
Hao Zhang35fa0dd2014-10-30 18:59:43 +0200565 .config = &m88e1518_config,
Michal Simek14151072012-10-15 14:03:00 +0200566 .startup = &m88e1011s_startup,
567 .shutdown = &genphy_shutdown,
568};
569
Sebastian Hesselbarthaeceec02012-12-04 09:31:59 +0100570static struct phy_driver M88E1310_driver = {
571 .name = "Marvell 88E1310",
572 .uid = 0x01410e90,
573 .mask = 0xffffff0,
574 .features = PHY_GBIT_FEATURES,
575 .config = &m88e1310_config,
576 .startup = &m88e1011s_startup,
577 .shutdown = &genphy_shutdown,
578};
579
Andy Fleming9082eea2011-04-07 21:56:05 -0500580int phy_marvell_init(void)
581{
Sebastian Hesselbarthaeceec02012-12-04 09:31:59 +0100582 phy_register(&M88E1310_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500583 phy_register(&M88E1149S_driver);
584 phy_register(&M88E1145_driver);
585 phy_register(&M88E1121R_driver);
586 phy_register(&M88E1118_driver);
Michal Simekb4b81e82012-08-07 02:23:07 +0000587 phy_register(&M88E1118R_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500588 phy_register(&M88E1111S_driver);
589 phy_register(&M88E1011S_driver);
Clemens Gruber8396d0a2015-06-06 14:44:58 +0200590 phy_register(&M88E1510_driver);
Michal Simek14151072012-10-15 14:03:00 +0200591 phy_register(&M88E1518_driver);
Andy Fleming9082eea2011-04-07 21:56:05 -0500592
593 return 0;
594}