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haikunddf79f32015-03-25 20:23:26 +08001/*
2 * Freescale ls1021a SOC common device tree source
3 *
4 * Copyright 2013-2015 Freescale Semiconductor, Inc.
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
haikunce35fc12015-03-24 21:16:31 +08009#include "skeleton.dtsi"
haikunddf79f32015-03-25 20:23:26 +080010#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13 compatible = "fsl,ls1021a";
14 interrupt-parent = <&gic>;
15
16 aliases {
17 serial0 = &lpuart0;
18 serial1 = &lpuart1;
19 serial2 = &lpuart2;
20 serial3 = &lpuart3;
21 serial4 = &lpuart4;
22 serial5 = &lpuart5;
23 sysclk = &sysclk;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@f00 {
31 compatible = "arm,cortex-a7";
32 device_type = "cpu";
33 reg = <0xf00>;
34 clocks = <&cluster1_clk>;
35 };
36
37 cpu@f01 {
38 compatible = "arm,cortex-a7";
39 device_type = "cpu";
40 reg = <0xf01>;
41 clocks = <&cluster1_clk>;
42 };
43 };
44
45 timer {
46 compatible = "arm,armv7-timer";
47 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
48 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
49 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
51 };
52
53 pmu {
54 compatible = "arm,cortex-a7-pmu";
55 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
57 };
58
59 soc {
60 compatible = "simple-bus";
haikunce35fc12015-03-24 21:16:31 +080061 #address-cells = <1>;
62 #size-cells = <1>;
haikunddf79f32015-03-25 20:23:26 +080063 device_type = "soc";
64 interrupt-parent = <&gic>;
65 ranges;
66
67 gic: interrupt-controller@1400000 {
68 compatible = "arm,cortex-a7-gic";
69 #interrupt-cells = <3>;
70 interrupt-controller;
haikunce35fc12015-03-24 21:16:31 +080071 reg = <0x1401000 0x1000>,
72 <0x1402000 0x1000>,
73 <0x1404000 0x2000>,
74 <0x1406000 0x2000>;
haikunddf79f32015-03-25 20:23:26 +080075 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
76
77 };
78
79 ifc: ifc@1530000 {
80 compatible = "fsl,ifc", "simple-bus";
haikunce35fc12015-03-24 21:16:31 +080081 reg = <0x1530000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +080082 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
83 };
84
85 dcfg: dcfg@1ee0000 {
86 compatible = "fsl,ls1021a-dcfg", "syscon";
haikunce35fc12015-03-24 21:16:31 +080087 reg = <0x1ee0000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +080088 big-endian;
89 };
90
91 esdhc: esdhc@1560000 {
92 compatible = "fsl,esdhc";
haikunce35fc12015-03-24 21:16:31 +080093 reg = <0x1560000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +080094 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
95 clock-frequency = <0>;
96 voltage-ranges = <1800 1800 3300 3300>;
97 sdhci,auto-cmd12;
98 big-endian;
99 bus-width = <4>;
100 status = "disabled";
101 };
102
103 scfg: scfg@1570000 {
104 compatible = "fsl,ls1021a-scfg", "syscon";
haikunce35fc12015-03-24 21:16:31 +0800105 reg = <0x1570000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800106 big-endian;
107 };
108
109 clockgen: clocking@1ee1000 {
110 #address-cells = <1>;
111 #size-cells = <1>;
haikunce35fc12015-03-24 21:16:31 +0800112 ranges = <0x0 0x1ee1000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800113
114 sysclk: sysclk {
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-output-names = "sysclk";
118 };
119
120 cga_pll1: pll@800 {
121 compatible = "fsl,qoriq-core-pll-2.0";
122 #clock-cells = <1>;
123 reg = <0x800 0x10>;
124 clocks = <&sysclk>;
125 clock-output-names = "cga-pll1", "cga-pll1-div2",
126 "cga-pll1-div4";
127 };
128
129 platform_clk: pll@c00 {
130 compatible = "fsl,qoriq-core-pll-2.0";
131 #clock-cells = <1>;
132 reg = <0xc00 0x10>;
133 clocks = <&sysclk>;
134 clock-output-names = "platform-clk", "platform-clk-div2";
135 };
136
137 cluster1_clk: clk0c0@0 {
138 compatible = "fsl,qoriq-core-mux-2.0";
139 #clock-cells = <0>;
140 reg = <0x0 0x10>;
141 clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
142 clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
143 clock-output-names = "cluster1-clk";
144 };
145 };
146
147 dspi0: dspi@2100000 {
148 compatible = "fsl,vf610-dspi";
149 #address-cells = <1>;
150 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800151 reg = <0x2100000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800152 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
153 clock-names = "dspi";
154 clocks = <&platform_clk 1>;
Haikun.Wang@freescale.com6db79c42015-03-24 21:19:23 +0800155 num-cs = <6>;
haikunddf79f32015-03-25 20:23:26 +0800156 big-endian;
157 status = "disabled";
158 };
159
160 dspi1: dspi@2110000 {
161 compatible = "fsl,vf610-dspi";
162 #address-cells = <1>;
163 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800164 reg = <0x2110000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800165 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
166 clock-names = "dspi";
167 clocks = <&platform_clk 1>;
Haikun.Wang@freescale.com6db79c42015-03-24 21:19:23 +0800168 num-cs = <6>;
haikunddf79f32015-03-25 20:23:26 +0800169 big-endian;
170 status = "disabled";
171 };
172
Haikun.Wang@freescale.com863b4e12015-03-24 21:20:40 +0800173 qspi: quadspi@1550000 {
174 compatible = "fsl,vf610-qspi";
175 #address-cells = <1>;
176 #size-cells = <0>;
177 reg = <0x1550000 0x10000>,
178 <0x40000000 0x4000000>;
179 num-cs = <2>;
180 big-endian;
181 status = "disabled";
182 };
183
haikunddf79f32015-03-25 20:23:26 +0800184 i2c0: i2c@2180000 {
185 compatible = "fsl,vf610-i2c";
186 #address-cells = <1>;
187 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800188 reg = <0x2180000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800189 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
190 clock-names = "i2c";
191 clocks = <&platform_clk 1>;
192 status = "disabled";
193 };
194
195 i2c1: i2c@2190000 {
196 compatible = "fsl,vf610-i2c";
197 #address-cells = <1>;
198 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800199 reg = <0x2190000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800200 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
201 clock-names = "i2c";
202 clocks = <&platform_clk 1>;
203 status = "disabled";
204 };
205
206 i2c2: i2c@21a0000 {
207 compatible = "fsl,vf610-i2c";
208 #address-cells = <1>;
209 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800210 reg = <0x21a0000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800211 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
212 clock-names = "i2c";
213 clocks = <&platform_clk 1>;
214 status = "disabled";
215 };
216
217 uart0: serial@21c0500 {
218 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800219 reg = <0x21c0500 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800220 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800221 fifo-size = <15>;
222 status = "disabled";
223 };
224
225 uart1: serial@21c0600 {
226 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800227 reg = <0x21c0600 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800228 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800229 fifo-size = <15>;
230 status = "disabled";
231 };
232
233 uart2: serial@21d0500 {
234 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800235 reg = <0x21d0500 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800236 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800237 fifo-size = <15>;
238 status = "disabled";
239 };
240
241 uart3: serial@21d0600 {
242 compatible = "fsl,16550-FIFO64", "ns16550a";
haikunce35fc12015-03-24 21:16:31 +0800243 reg = <0x21d0600 0x100>;
haikunddf79f32015-03-25 20:23:26 +0800244 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
haikunddf79f32015-03-25 20:23:26 +0800245 fifo-size = <15>;
246 status = "disabled";
247 };
248
249 lpuart0: serial@2950000 {
250 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800251 reg = <0x2950000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800252 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&sysclk>;
254 clock-names = "ipg";
255 status = "disabled";
256 };
257
258 lpuart1: serial@2960000 {
259 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800260 reg = <0x2960000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800261 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&platform_clk 1>;
263 clock-names = "ipg";
264 status = "disabled";
265 };
266
267 lpuart2: serial@2970000 {
268 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800269 reg = <0x2970000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800270 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
271 clocks = <&platform_clk 1>;
272 clock-names = "ipg";
273 status = "disabled";
274 };
275
276 lpuart3: serial@2980000 {
277 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800278 reg = <0x2980000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800279 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
280 clocks = <&platform_clk 1>;
281 clock-names = "ipg";
282 status = "disabled";
283 };
284
285 lpuart4: serial@2990000 {
286 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800287 reg = <0x2990000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800288 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&platform_clk 1>;
290 clock-names = "ipg";
291 status = "disabled";
292 };
293
294 lpuart5: serial@29a0000 {
295 compatible = "fsl,ls1021a-lpuart";
haikunce35fc12015-03-24 21:16:31 +0800296 reg = <0x29a0000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800297 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&platform_clk 1>;
299 clock-names = "ipg";
300 status = "disabled";
301 };
302
303 wdog0: watchdog@2ad0000 {
304 compatible = "fsl,imx21-wdt";
haikunce35fc12015-03-24 21:16:31 +0800305 reg = <0x2ad0000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800306 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&platform_clk 1>;
308 clock-names = "wdog-en";
309 big-endian;
310 };
311
312 sai1: sai@2b50000 {
313 compatible = "fsl,vf610-sai";
haikunce35fc12015-03-24 21:16:31 +0800314 reg = <0x2b50000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800315 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&platform_clk 1>;
317 clock-names = "sai";
318 dma-names = "tx", "rx";
319 dmas = <&edma0 1 47>,
320 <&edma0 1 46>;
321 big-endian;
322 status = "disabled";
323 };
324
325 sai2: sai@2b60000 {
326 compatible = "fsl,vf610-sai";
haikunce35fc12015-03-24 21:16:31 +0800327 reg = <0x2b60000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800328 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&platform_clk 1>;
330 clock-names = "sai";
331 dma-names = "tx", "rx";
332 dmas = <&edma0 1 45>,
333 <&edma0 1 44>;
334 big-endian;
335 status = "disabled";
336 };
337
338 edma0: edma@2c00000 {
339 #dma-cells = <2>;
340 compatible = "fsl,vf610-edma";
haikunce35fc12015-03-24 21:16:31 +0800341 reg = <0x2c00000 0x10000>,
342 <0x2c10000 0x10000>,
343 <0x2c20000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800344 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
346 interrupt-names = "edma-tx", "edma-err";
347 dma-channels = <32>;
348 big-endian;
349 clock-names = "dmamux0", "dmamux1";
350 clocks = <&platform_clk 1>,
351 <&platform_clk 1>;
352 };
353
354 mdio0: mdio@2d24000 {
355 compatible = "gianfar";
356 device_type = "mdio";
357 #address-cells = <1>;
358 #size-cells = <0>;
haikunce35fc12015-03-24 21:16:31 +0800359 reg = <0x2d24000 0x4000>;
haikunddf79f32015-03-25 20:23:26 +0800360 };
361
362 usb@8600000 {
363 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
haikunce35fc12015-03-24 21:16:31 +0800364 reg = <0x8600000 0x1000>;
haikunddf79f32015-03-25 20:23:26 +0800365 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
366 dr_mode = "host";
367 phy_type = "ulpi";
368 };
369
370 usb3@3100000 {
Rajesh Bhagata866c212016-07-01 18:51:48 +0530371 compatible = "fsl,layerscape-dwc3";
haikunce35fc12015-03-24 21:16:31 +0800372 reg = <0x3100000 0x10000>;
haikunddf79f32015-03-25 20:23:26 +0800373 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
374 dr_mode = "host";
375 };
376 };
377};