blob: 5bdefb8a0d1d627a302d5d918f23826208e49f4e [file] [log] [blame]
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04001/*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
5 * original copyright follows:
6 * Copyright 2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11#include <common.h>
12#include <ns16550.h>
13#include <asm/io.h>
14#include <nand.h>
15#include <linux/compiler.h>
16#include <asm/fsl_law.h>
17#include <fsl_ddr_sdram.h>
18#include <asm/global_data.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22void board_init_f(ulong bootflag)
23{
24 u32 plat_ratio;
25 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
26
27#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
28 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
29 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
30#endif
31
32 /* initialize selected port with appropriate baud rate */
33 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
34 plat_ratio >>= 1;
35 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
36
37 NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
38 gd->bus_clk / 16 / CONFIG_BAUDRATE);
39
40 puts("\nNAND boot... ");
41
42 /* copy code to RAM and jump to it - this should not return */
43 /* NOTE - code has to be copied out of NAND buffer before
44 * other blocks can be read.
45 */
46 relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
47}
48
49void board_init_r(gd_t *gd, ulong dest_addr)
50{
51 puts("\nSecond program loader running in sram...");
52 nand_boot();
53}
54
55void putc(char c)
56{
57 if (c == '\n')
58 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
59
60 NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
61}
62
63void puts(const char *str)
64{
65 while (*str)
66 putc(*str++);
67}