Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 2 | /* |
Tony Dinh | 648f8d5 | 2022-01-25 19:33:44 -0800 | [diff] [blame] | 3 | * Copyright (C) 2021-2022 Tony Dinh <mibodhi@gmail.com> |
| 4 | * Copyright (C) 2013-2021 Suriyan Ramasami <suriyan.r@gmail.com> |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 5 | * |
| 6 | * Based on dockstar.c originally written by |
| 7 | * Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu> |
| 8 | * |
| 9 | * Based on sheevaplug.c originally written by |
| 10 | * Prafulla Wadaskar <prafulla@marvell.com> |
| 11 | * (C) Copyright 2009 |
| 12 | * Marvell Semiconductor <www.marvell.com> |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 13 | */ |
| 14 | |
| 15 | #include <common.h> |
Simon Glass | 52f2423 | 2020-05-10 11:40:00 -0600 | [diff] [blame] | 16 | #include <bootstage.h> |
Simon Glass | 691d719 | 2020-05-10 11:40:02 -0600 | [diff] [blame] | 17 | #include <init.h> |
Tony Dinh | 648f8d5 | 2022-01-25 19:33:44 -0800 | [diff] [blame] | 18 | #include <netdev.h> |
Simon Glass | 401d1c4 | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 19 | #include <asm/global_data.h> |
Simon Glass | c62db35 | 2017-05-31 19:47:48 -0600 | [diff] [blame] | 20 | #include <asm/mach-types.h> |
Stefan Roese | 3dc23f7 | 2014-10-22 12:13:06 +0200 | [diff] [blame] | 21 | #include <asm/arch/soc.h> |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 22 | #include <asm/arch/mpp.h> |
| 23 | #include <asm/arch/cpu.h> |
| 24 | #include <asm/io.h> |
Tony Dinh | 648f8d5 | 2022-01-25 19:33:44 -0800 | [diff] [blame] | 25 | #include <linux/bitops.h> |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | int board_early_init_f(void) |
| 30 | { |
| 31 | /* Multi-Purpose Pins Functionality configuration */ |
| 32 | static const u32 kwmpp_config[] = { |
| 33 | MPP0_NF_IO2, |
| 34 | MPP1_NF_IO3, |
| 35 | MPP2_NF_IO4, |
| 36 | MPP3_NF_IO5, |
| 37 | MPP4_NF_IO6, |
| 38 | MPP5_NF_IO7, |
| 39 | MPP6_SYSRST_OUTn, |
| 40 | MPP7_GPO, |
| 41 | MPP8_UART0_RTS, |
| 42 | MPP9_UART0_CTS, |
| 43 | MPP10_UART0_TXD, |
| 44 | MPP11_UART0_RXD, |
| 45 | MPP12_SD_CLK, |
| 46 | MPP13_SD_CMD, |
| 47 | MPP14_SD_D0, |
| 48 | MPP15_SD_D1, |
| 49 | MPP16_SD_D2, |
| 50 | MPP17_SD_D3, |
| 51 | MPP18_NF_IO0, |
| 52 | MPP19_NF_IO1, |
| 53 | MPP20_GPIO, |
| 54 | MPP21_GPIO, |
| 55 | MPP22_GPIO, |
| 56 | MPP23_GPIO, |
| 57 | MPP24_GPIO, |
| 58 | MPP25_GPIO, |
| 59 | MPP26_GPIO, |
| 60 | MPP27_GPIO, |
| 61 | MPP28_GPIO, |
| 62 | MPP29_TSMP9, |
| 63 | MPP30_GPIO, |
| 64 | MPP31_GPIO, |
| 65 | MPP32_GPIO, |
| 66 | MPP33_GPIO, |
| 67 | MPP34_GPIO, |
| 68 | MPP35_GPIO, |
| 69 | MPP36_GPIO, |
| 70 | MPP37_GPIO, |
| 71 | MPP38_GPIO, |
| 72 | MPP39_GPIO, |
| 73 | MPP40_GPIO, |
| 74 | MPP41_GPIO, |
| 75 | MPP42_GPIO, |
| 76 | MPP43_GPIO, |
| 77 | MPP44_GPIO, |
| 78 | MPP45_GPIO, |
| 79 | MPP46_GPIO, |
| 80 | MPP47_GPIO, |
| 81 | MPP48_GPIO, |
| 82 | MPP49_GPIO, |
| 83 | 0 |
| 84 | }; |
| 85 | |
| 86 | /* |
| 87 | * default gpio configuration |
| 88 | * There are maximum 64 gpios controlled through 2 sets of registers |
| 89 | * the below configuration configures mainly initial LED status |
| 90 | */ |
Stefan Roese | d5c5132 | 2014-10-22 12:13:11 +0200 | [diff] [blame] | 91 | mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW, |
| 92 | GOFLEXHOME_OE_VAL_HIGH, |
| 93 | GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH); |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 94 | kirkwood_mpp_conf(kwmpp_config, NULL); |
| 95 | return 0; |
| 96 | } |
| 97 | |
Tony Dinh | 648f8d5 | 2022-01-25 19:33:44 -0800 | [diff] [blame] | 98 | int board_eth_init(struct bd_info *bis) |
| 99 | { |
| 100 | return cpu_eth_init(bis); |
| 101 | } |
| 102 | |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 103 | int board_init(void) |
| 104 | { |
Tom Rini | 94ba26f | 2017-01-25 20:42:35 -0500 | [diff] [blame] | 105 | /* |
| 106 | * arch number of board |
| 107 | */ |
| 108 | gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME; |
| 109 | |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 110 | /* address of boot parameters */ |
Stefan Roese | 96c5f08 | 2014-10-22 12:13:13 +0200 | [diff] [blame] | 111 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 112 | |
| 113 | return 0; |
| 114 | } |
| 115 | |
Tom Rini | cb80ff2 | 2021-05-03 16:48:58 -0400 | [diff] [blame] | 116 | #if CONFIG_IS_ENABLED(BOOTSTAGE) |
Tony Dinh | 648f8d5 | 2022-01-25 19:33:44 -0800 | [diff] [blame] | 117 | #define GREEN_LED BIT(14) |
| 118 | #define ORANGE_LED BIT(15) |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 119 | #define BOTH_LEDS (GREEN_LED | ORANGE_LED) |
| 120 | #define NEITHER_LED 0 |
| 121 | |
| 122 | static void set_leds(u32 leds, u32 blinking) |
| 123 | { |
| 124 | struct kwgpio_registers *r; |
| 125 | u32 oe; |
| 126 | u32 bl; |
| 127 | |
Stefan Roese | d5c5132 | 2014-10-22 12:13:11 +0200 | [diff] [blame] | 128 | r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE; |
Suriyan Ramasami | 0ad6c34 | 2013-04-11 07:17:25 +0000 | [diff] [blame] | 129 | oe = readl(&r->oe) | BOTH_LEDS; |
| 130 | writel(oe & ~leds, &r->oe); /* active low */ |
| 131 | bl = readl(&r->blink_en) & ~BOTH_LEDS; |
| 132 | writel(bl | blinking, &r->blink_en); |
| 133 | } |
| 134 | |
| 135 | void show_boot_progress(int val) |
| 136 | { |
| 137 | switch (val) { |
| 138 | case BOOTSTAGE_ID_RUN_OS: /* booting Linux */ |
| 139 | set_leds(BOTH_LEDS, NEITHER_LED); |
| 140 | break; |
| 141 | case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */ |
| 142 | set_leds(GREEN_LED, GREEN_LED); |
| 143 | break; |
| 144 | default: |
| 145 | if (val < 0) /* error */ |
| 146 | set_leds(ORANGE_LED, ORANGE_LED); |
| 147 | break; |
| 148 | } |
| 149 | } |
Tom Rini | cb80ff2 | 2021-05-03 16:48:58 -0400 | [diff] [blame] | 150 | #endif |